`define FMC_ADC_100MS_CHANNEL_REGS_SIZE 24
`define ADDR_FMC_ADC_100MS_CHANNEL_REGS_CTL 'h0
`define FMC_ADC_100MS_CHANNEL_REGS_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CHANNEL_REGS_CTL_SSR 'h7f
`define ADDR_FMC_ADC_100MS_CHANNEL_REGS_STA 'h4
`define FMC_ADC_100MS_CHANNEL_REGS_STA_VAL_OFFSET 0
`define FMC_ADC_100MS_CHANNEL_REGS_STA_VAL 'hffff
`define ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB 'h8
`define FMC_ADC_100MS_CHANNEL_REGS_CALIB_GAIN_OFFSET 0
`define FMC_ADC_100MS_CHANNEL_REGS_CALIB_GAIN 'hffff
`define FMC_ADC_100MS_CHANNEL_REGS_CALIB_OFFSET_OFFSET 16
`define FMC_ADC_100MS_CHANNEL_REGS_CALIB_OFFSET 'hffff0000
`define ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT 'hc
`define FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL_OFFSET 0
`define FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL 'h7fff
`define ADDR_FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES 'h10
`define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_VAL_OFFSET 0
`define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_VAL 'hffff
`define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_HYST 'hffff0000
`define ADDR_FMC_ADC_100MS_CHANNEL_REGS_TRIG_DLY 'h14
