This design is targeted for xczu7cg board (part number: xczu7cg-ffvf1517-1-e)

Zynq UltraScale+ Design Summary

Device	xczu7cg
SpeedGrade	-1
Part	xczu7cg-ffvf1517-1-e
Description	Zynq UltraScale+ PS Configuration Report
Vendor	Xilinx

MIO Table View

MIO Pin	Peripheral	Signal	IO Type	Speed	Pullup	Direction	Drive Strength(mA)
MIO 0	Quad SPI Flash	sclk_out	cmos	fast	pullup	out	12
MIO 1	Quad SPI Flash	miso_mo1	cmos	fast	pullup	inout	12
MIO 2	Quad SPI Flash	mo2	cmos	fast	pullup	inout	12
MIO 3	Quad SPI Flash	mo3	cmos	fast	pullup	inout	12
MIO 4	Quad SPI Flash	mosi_mi0	cmos	fast	pullup	inout	12
MIO 5	Quad SPI Flash	n_ss_out	cmos	fast	pullup	out	12
MIO 6			cmos	fast	pullup		12
MIO 7	Quad SPI Flash	n_ss_out_upper	cmos	fast	pullup	out	12
MIO 8	Quad SPI Flash	mo_upper[0]	cmos	fast	pullup	inout	12
MIO 9	Quad SPI Flash	mo_upper[1]	cmos	fast	pullup	inout	12
MIO 10	Quad SPI Flash	mo_upper[2]	cmos	fast	pullup	inout	12
MIO 11	Quad SPI Flash	mo_upper[3]	cmos	fast	pullup	inout	12
MIO 12	Quad SPI Flash	sclk_out_upper	cmos	fast	pullup	out	12
MIO 13	SD 0	sdio0_data_out[0]	cmos	fast	pullup	inout	12
MIO 14	SD 0	sdio0_data_out[1]	cmos	fast	pullup	inout	12
MIO 15	SD 0	sdio0_data_out[2]	cmos	fast	pullup	inout	12
MIO 16	SD 0	sdio0_data_out[3]	cmos	fast	pullup	inout	12
MIO 17	SD 0	sdio0_data_out[4]	cmos	fast	pullup	inout	12
MIO 18	SD 0	sdio0_data_out[5]	cmos	fast	pullup	inout	12
MIO 19	SD 0	sdio0_data_out[6]	cmos	fast	pullup	inout	12
MIO 20	SD 0	sdio0_data_out[7]	cmos	fast	pullup	inout	12
MIO 21	SD 0	sdio0_cmd_out	cmos	fast	pullup	inout	12
MIO 22	SD 0	sdio0_clk_out	cmos	fast	pullup	out	12
MIO 23			cmos	fast	pullup		12
MIO 24			cmos	fast	pullup		12
MIO 25			cmos	fast	pullup		12
MIO 26			cmos	fast	pullup		12
MIO 27			cmos	fast	pullup		12
MIO 28			cmos	fast	pullup		12
MIO 29			cmos	fast	pullup	in	12
MIO 30	UART 0	rxd	cmos	fast	pullup	in	12
MIO 31	UART 0	txd	cmos	fast	pullup	out	12
MIO 32			cmos	fast	pullup		12
MIO 33			cmos	fast	pullup		12
MIO 34			cmos	fast	pullup		12
MIO 35			cmos	fast	pullup	in	12
MIO 36	PCIE	reset_n	schmitt	fast	pullup	in	12
MIO 37			cmos	fast	pullup		12
MIO 38			cmos	fast	pullup		12
MIO 39			cmos	fast	pullup		12
MIO 40			cmos	fast	pullup		12
MIO 41			cmos	fast	pullup		12
MIO 42			cmos	fast	pullup		12
MIO 43			cmos	fast	pullup		12
MIO 44			cmos	fast	pullup		12
MIO 45			cmos	fast	pullup		12
MIO 46			cmos	fast	pullup		12
MIO 47			cmos	fast	pullup		12
MIO 48			cmos	fast	pullup		12
MIO 49			cmos	fast	pullup		12
MIO 50			cmos	fast	pullup		12
MIO 51			cmos	fast	pullup		12
MIO 52			cmos	fast	pullup		12
MIO 53			cmos	fast	pullup		12
MIO 54			cmos	fast	pullup		12
MIO 55			cmos	fast	pullup		12
MIO 56			cmos	fast	pullup		12
MIO 57			cmos	fast	pullup		12
MIO 58			cmos	fast	pullup		12
MIO 59			cmos	fast	pullup		12
MIO 60			cmos	fast	pullup		12
MIO 61			cmos	fast	pullup		12
MIO 62			cmos	fast	pullup		12
MIO 63			cmos	fast	pullup		12
MIO 64			cmos	fast	pullup		12
MIO 65			cmos	fast	pullup		12
MIO 66			cmos	fast	pullup		12
MIO 67			cmos	fast	pullup		12
MIO 68			cmos	fast	pullup		12
MIO 69			cmos	fast	pullup		12
MIO 70			cmos	fast	pullup		12
MIO 71			cmos	fast	pullup		12
MIO 72			cmos	fast	pullup		12
MIO 73			cmos	fast	pullup		12
MIO 74			cmos	fast	pullup		12
MIO 75			cmos	fast	pullup		12
MIO 76			cmos	fast	pullup		12
MIO 77			cmos	fast	pullup		12

PS Clocks information

PSS REF CLK : 33.333

Name	Source	Input Frequency (MHz)
APLL	PSS_REF_CLK	2399.976
DPLL	PSS_REF_CLK	2399.976
VPLL	PSS_REF_CLK	2133.312
RPLL	PSS_REF_CLK	1599.984
IOPLL	PSS_REF_CLK	2999.970

Peripheral	Requested Frequency (MHz)	Source	Actual Frequency (MHz)
QSPI freq (MHz)	300	IOPLL	299.997009
SDIO0 freq (MHz)	200	RPLL	199.998001
UART0 freq (MHz)	100	IOPLL	99.999001
I2C0 freq (MHz)	100	IOPLL	99.999001
CPU_R5 freq (MHz)	500	IOPLL	499.994995
IOU_SWITCH freq (MHz)	267	RPLL	266.664001
LPD_SWITCH freq (MHz)	500	IOPLL	499.994995
LPD_LSBUS freq (MHz)	100	IOPLL	99.999001
TIMESTAMP freq (MHz)	100	PSS_REF_CLK	33.333000
PCAP freq (MHz)	200	IOPLL	187.498123
DBG_LPD freq (MHz)	250	IOPLL	249.997498
ADMA freq (MHz)	500	IOPLL	499.994995
AMS freq (MHz)	50	IOPLL	49.999500
ACPU freq (MHz)	1200	APLL	1199.988037
DBG FPD freq (MHz)	250	IOPLL	249.997498
PCIE freq (MHz)	250	IOPLL	249.997498
DDR_CTRL freq MHz)	600.000	DPLL	599.994019
GDMA freq (MHz)	600	DPLL	599.994019
DPDMA freq (MHz)	600	DPLL	599.994019
TOPSW_MAIN freq (MHz)	533.333	VPLL	533.328003
TOPSW_LSBUS freq (MHz)	100	IOPLL	99.999001
DBG TSTMP freq (MHz)	250	IOPLL	249.997498

DDR Memory information

Parameter name	Value	Description
ENABLE	1	Enable the PS DDR Controller
DDR Interface freq (MHz)	1200	--
MEMORY TYPE	DDR 4	Type of memory interface
DM DBI	Components
BUS WIDTH	64 Bit	Data width of DDR interface, not including ECC data width
ECC	Enabled	Enables error correction code support
SPEED BIN	DDR4_2400P	Speed Bin
CL	17	Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module
CWL	12	CAS write latency setting in memory clock cycles
DDR AL	0	Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
T RCD	17	tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
T RP	17	Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row
T RC	46.16	Row cycle time (ns)
T RAS MIN	32	Minimum number of memory clock cycles required between an Active and Precharge command
T FAW	30.0	Determines the number of activates that can be performed within a certain window of time
DRAM WIDTH	16 Bits	Width of individual DRAM components
DEVICE CAPACITY	8192 MBits	Storage capacity of individual DRAM components
BG ADDR COUNT	1	Number of bank group address pins
RANK ADDR COUNT	0	Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N)
BANK ADDR COUNT	2	Number of bank address pins
ROW ADDR COUNT	16	Number of row address pins
COL ADDR COUNT	10	Number of column address bits
C_DDR_RAM_HIGHADDR	0xFFFFFFFF	--

GT lanes information

Protocol	GT lane#	Ref Clk Sel	Ref freq (MHz)
PCIe	GT Lane0	Ref Clk0	100