== Memory map summary
FMC ADC alt trigger out registers

|===
|HW address | Type | Name | HDL name

|0x00
|REG
|status
|status

|0x08
|REG
|ts_mask_sec
|ts_mask_sec

|0x10
|REG
|ts_cycles
|ts_cycles
|===

== Registers description
=== status
[horizontal]
HDL name:: status
address:: 0x0
block offset:: 0x0
access mode:: ro

Status register

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

| -
| -
| -
| -
| -
| -
| -
| -

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

| -
| -
| -
| -
| -
| -
| -
| -

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

| -
| -
| -
| -
| -
| -
| -
s| ts_present

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

| -
| -
| -
| -
| -
s| wr_valid
s| wr_link
s| wr_enable
|===

wr_enable:: Set when WR is enabled
wr_link:: WR link status
wr_valid:: Set when WR time is valid
ts_present:: Set when the timestamp fifo is not empty

=== ts_mask_sec
[horizontal]
HDL name:: ts_mask_sec
address:: 0x8
block offset:: 0x8
access mode:: ro

Time (seconds) of the last event

[cols="8*^"]
|===

| 63
| 62
| 61
| 60
| 59
| 58
| 57
| 56

| -
| -
| -
| -
| -
| -
| -
s| ext_mask

| 55
| 54
| 53
| 52
| 51
| 50
| 49
| 48

| -
| -
| -
| -
s| ch4_mask
s| ch3_mask
s| ch2_mask
s| ch1_mask

| 47
| 46
| 45
| 44
| 43
| 42
| 41
| 40

| -
| -
| -
| -
| -
| -
| -
| -

| 39
| 38
| 37
| 36
| 35
| 34
| 33
| 32

8+s| ts_sec[39:32]

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

8+s| ts_sec[31:24]

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

8+s| ts_sec[23:16]

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

8+s| ts_sec[15:8]

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| ts_sec[7:0]
|===

ts_sec:: Seconds part of the timestamp
ch1_mask:: Set if channel 1 triggered
ch2_mask:: Set if channel 2 triggered
ch3_mask:: Set if channel 3 triggered
ch4_mask:: Set if channel 4 triggered
ext_mask:: Set if external trigger

=== ts_cycles
[horizontal]
HDL name:: ts_cycles
address:: 0x10
block offset:: 0x10
access mode:: ro

Cycles part of timestamp fifo.

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

| -
| -
| -
| -
4+s| cycles[27:24]

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

8+s| cycles[23:16]

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

8+s| cycles[15:8]

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| cycles[7:0]
|===

cycles:: Cycles

