== Memory map summary
Time-tagging core registers

|===
|HW address | Type | Name | HDL name

|0x00
|REG
|seconds_upper
|seconds_upper

|0x04
|REG
|seconds_lower
|seconds_lower

|0x08
|REG
|coarse
|coarse

|0x0c
|REG
|time_trig_seconds_upper
|time_trig_seconds_upper

|0x10
|REG
|time_trig_seconds_lower
|time_trig_seconds_lower

|0x14
|REG
|time_trig_coarse
|time_trig_coarse

|0x18
|REG
|trig_tag_seconds_upper
|trig_tag_seconds_upper

|0x1c
|REG
|trig_tag_seconds_lower
|trig_tag_seconds_lower

|0x20
|REG
|trig_tag_coarse
|trig_tag_coarse

|0x24
|REG
|acq_start_tag_seconds_upper
|acq_start_tag_seconds_upper

|0x28
|REG
|acq_start_tag_seconds_lower
|acq_start_tag_seconds_lower

|0x2c
|REG
|acq_start_tag_coarse
|acq_start_tag_coarse

|0x30
|REG
|acq_stop_tag_seconds_upper
|acq_stop_tag_seconds_upper

|0x34
|REG
|acq_stop_tag_seconds_lower
|acq_stop_tag_seconds_lower

|0x38
|REG
|acq_stop_tag_coarse
|acq_stop_tag_coarse

|0x3c
|REG
|acq_end_tag_seconds_upper
|acq_end_tag_seconds_upper

|0x40
|REG
|acq_end_tag_seconds_lower
|acq_end_tag_seconds_lower

|0x44
|REG
|acq_end_tag_coarse
|acq_end_tag_coarse
|===

== Registers description
=== seconds_upper
[horizontal]
HDL name:: seconds_upper
address:: 0x0
block offset:: 0x0
access mode:: rw

Timetag seconds register (upper)

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

| -
| -
| -
| -
| -
| -
| -
| -

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

| -
| -
| -
| -
| -
| -
| -
| -

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

| -
| -
| -
| -
| -
| -
| -
| -

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| seconds_upper[7:0]
|===

:: Timetag seconds

=== seconds_lower
[horizontal]
HDL name:: seconds_lower
address:: 0x4
block offset:: 0x4
access mode:: rw

Timetag seconds register (lower)

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

8+s| seconds_lower[31:24]

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

8+s| seconds_lower[23:16]

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

8+s| seconds_lower[15:8]

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| seconds_lower[7:0]
|===
=== coarse
[horizontal]
HDL name:: coarse
address:: 0x8
block offset:: 0x8
access mode:: rw

Timetag coarse time register, system clock ticks (125MHz)

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

| -
| -
| -
| -
4+s| coarse[27:24]

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

8+s| coarse[23:16]

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

8+s| coarse[15:8]

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| coarse[7:0]
|===

:: Timetag coarse time

=== time_trig_seconds_upper
[horizontal]
HDL name:: time_trig_seconds_upper
address:: 0xc
block offset:: 0xc
access mode:: rw

Time trigger seconds register (upper)

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

| -
| -
| -
| -
| -
| -
| -
| -

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

| -
| -
| -
| -
| -
| -
| -
| -

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

| -
| -
| -
| -
| -
| -
| -
| -

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| time_trig_seconds_upper[7:0]
|===

:: Time trigger seconds

=== time_trig_seconds_lower
[horizontal]
HDL name:: time_trig_seconds_lower
address:: 0x10
block offset:: 0x10
access mode:: rw

Time trigger seconds register (lower)

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

8+s| time_trig_seconds_lower[31:24]

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

8+s| time_trig_seconds_lower[23:16]

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

8+s| time_trig_seconds_lower[15:8]

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| time_trig_seconds_lower[7:0]
|===
=== time_trig_coarse
[horizontal]
HDL name:: time_trig_coarse
address:: 0x14
block offset:: 0x14
access mode:: rw

Time trigger coarse time register, system clock ticks (125MHz)

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

| -
| -
| -
| -
4+s| time_trig_coarse[27:24]

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

8+s| time_trig_coarse[23:16]

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

8+s| time_trig_coarse[15:8]

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| time_trig_coarse[7:0]
|===

:: Time trigger coarse value

=== trig_tag_seconds_upper
[horizontal]
HDL name:: trig_tag_seconds_upper
address:: 0x18
block offset:: 0x18
access mode:: ro

Trigger time-tag seconds register (upper)

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

| -
| -
| -
| -
| -
| -
| -
| -

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

| -
| -
| -
| -
| -
| -
| -
| -

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

| -
| -
| -
| -
| -
| -
| -
| -

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| trig_tag_seconds_upper[7:0]
|===

:: Holds time-tag seconds of the last trigger event

=== trig_tag_seconds_lower
[horizontal]
HDL name:: trig_tag_seconds_lower
address:: 0x1c
block offset:: 0x1c
access mode:: ro

Trigger time-tag seconds register (lower)

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

8+s| trig_tag_seconds_lower[31:24]

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

8+s| trig_tag_seconds_lower[23:16]

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

8+s| trig_tag_seconds_lower[15:8]

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| trig_tag_seconds_lower[7:0]
|===
=== trig_tag_coarse
[horizontal]
HDL name:: trig_tag_coarse
address:: 0x20
block offset:: 0x20
access mode:: ro

Trigger time-tag coarse time (system clock ticks 125MHz) register

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

| -
| -
| -
| -
4+s| trig_tag_coarse[27:24]

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

8+s| trig_tag_coarse[23:16]

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

8+s| trig_tag_coarse[15:8]

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| trig_tag_coarse[7:0]
|===

:: Holds time-tag coarse time of the last trigger event

=== acq_start_tag_seconds_upper
[horizontal]
HDL name:: acq_start_tag_seconds_upper
address:: 0x24
block offset:: 0x24
access mode:: ro

Acquisition start time-tag seconds register (upper)

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

| -
| -
| -
| -
| -
| -
| -
| -

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

| -
| -
| -
| -
| -
| -
| -
| -

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

| -
| -
| -
| -
| -
| -
| -
| -

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| acq_start_tag_seconds_upper[7:0]
|===

:: Holds time-tag seconds of the last acquisition start event

=== acq_start_tag_seconds_lower
[horizontal]
HDL name:: acq_start_tag_seconds_lower
address:: 0x28
block offset:: 0x28
access mode:: ro

Acquisition start time-tag seconds register (lower)

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

8+s| acq_start_tag_seconds_lower[31:24]

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

8+s| acq_start_tag_seconds_lower[23:16]

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

8+s| acq_start_tag_seconds_lower[15:8]

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| acq_start_tag_seconds_lower[7:0]
|===
=== acq_start_tag_coarse
[horizontal]
HDL name:: acq_start_tag_coarse
address:: 0x2c
block offset:: 0x2c
access mode:: ro

Acquisition start time-tag coarse time (system clock ticks 125MHz) register

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

| -
| -
| -
| -
4+s| acq_start_tag_coarse[27:24]

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

8+s| acq_start_tag_coarse[23:16]

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

8+s| acq_start_tag_coarse[15:8]

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| acq_start_tag_coarse[7:0]
|===

:: Holds time-tag coarse time of the last acquisition start event

=== acq_stop_tag_seconds_upper
[horizontal]
HDL name:: acq_stop_tag_seconds_upper
address:: 0x30
block offset:: 0x30
access mode:: ro

Acquisition stop time-tag seconds register (upper)

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

| -
| -
| -
| -
| -
| -
| -
| -

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

| -
| -
| -
| -
| -
| -
| -
| -

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

| -
| -
| -
| -
| -
| -
| -
| -

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| acq_stop_tag_seconds_upper[7:0]
|===

:: Holds time-tag seconds of the last acquisition stop event

=== acq_stop_tag_seconds_lower
[horizontal]
HDL name:: acq_stop_tag_seconds_lower
address:: 0x34
block offset:: 0x34
access mode:: ro

Acquisition stop time-tag seconds register (lower)

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

8+s| acq_stop_tag_seconds_lower[31:24]

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

8+s| acq_stop_tag_seconds_lower[23:16]

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

8+s| acq_stop_tag_seconds_lower[15:8]

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| acq_stop_tag_seconds_lower[7:0]
|===
=== acq_stop_tag_coarse
[horizontal]
HDL name:: acq_stop_tag_coarse
address:: 0x38
block offset:: 0x38
access mode:: ro

Acquisition stop time-tag coarse time (system clock ticks 125MHz) register

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

| -
| -
| -
| -
4+s| acq_stop_tag_coarse[27:24]

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

8+s| acq_stop_tag_coarse[23:16]

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

8+s| acq_stop_tag_coarse[15:8]

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| acq_stop_tag_coarse[7:0]
|===

:: Holds time-tag coarse time of the last acquisition stop event

=== acq_end_tag_seconds_upper
[horizontal]
HDL name:: acq_end_tag_seconds_upper
address:: 0x3c
block offset:: 0x3c
access mode:: ro

Acquisition end time-tag seconds register (upper)

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

| -
| -
| -
| -
| -
| -
| -
| -

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

| -
| -
| -
| -
| -
| -
| -
| -

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

| -
| -
| -
| -
| -
| -
| -
| -

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| acq_end_tag_seconds_upper[7:0]
|===

:: Holds time-tag seconds of the last acquisition end event

=== acq_end_tag_seconds_lower
[horizontal]
HDL name:: acq_end_tag_seconds_lower
address:: 0x40
block offset:: 0x40
access mode:: ro

Acquisition end time-tag seconds register (lower)

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

8+s| acq_end_tag_seconds_lower[31:24]

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

8+s| acq_end_tag_seconds_lower[23:16]

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

8+s| acq_end_tag_seconds_lower[15:8]

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| acq_end_tag_seconds_lower[7:0]
|===
=== acq_end_tag_coarse
[horizontal]
HDL name:: acq_end_tag_coarse
address:: 0x44
block offset:: 0x44
access mode:: ro

Acquisition end time-tag coarse time (system clock ticks 125MHz) register

[cols="8*^"]
|===

| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24

| -
| -
| -
| -
4+s| acq_end_tag_coarse[27:24]

| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16

8+s| acq_end_tag_coarse[23:16]

| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8

8+s| acq_end_tag_coarse[15:8]

| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0

8+s| acq_end_tag_coarse[7:0]
|===

:: Holds time-tag coarse time of the last acquisition end event

