/*
  Register definitions for slave core: Interrupt controller

  * File           : irq_controller.h
  * Author         : auto-generated by wbgen2 from irq_controller.wb
  * Created        : Mon Jul 22 11:13:45 2013
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_IRQ_CONTROLLER_WB
#define __WBGEN2_REGDEFS_IRQ_CONTROLLER_WB

#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: Interrupt disable register */

/* definitions for field: FMC slot 1 trigger interrupt in reg: Interrupt disable register */
#define IRQ_CTRL_EIC_IDR_FMC0_TRIG            WBGEN2_GEN_MASK(0, 1)

/* definitions for field: FMC slot 1 end of acquisition interrupt in reg: Interrupt disable register */
#define IRQ_CTRL_EIC_IDR_FMC0_ACQ_END         WBGEN2_GEN_MASK(1, 1)

/* definitions for field: FMC slot 2 trigger interrupt in reg: Interrupt disable register */
#define IRQ_CTRL_EIC_IDR_FMC1_TRIG            WBGEN2_GEN_MASK(2, 1)

/* definitions for field: FMC slot 2 end of acquisition interrupt in reg: Interrupt disable register */
#define IRQ_CTRL_EIC_IDR_FMC1_ACQ_END         WBGEN2_GEN_MASK(3, 1)

/* definitions for register: Interrupt enable register */

/* definitions for field: FMC slot 1 trigger interrupt in reg: Interrupt enable register */
#define IRQ_CTRL_EIC_IER_FMC0_TRIG            WBGEN2_GEN_MASK(0, 1)

/* definitions for field: FMC slot 1 end of acquisition interrupt in reg: Interrupt enable register */
#define IRQ_CTRL_EIC_IER_FMC0_ACQ_END         WBGEN2_GEN_MASK(1, 1)

/* definitions for field: FMC slot 2 trigger interrupt in reg: Interrupt enable register */
#define IRQ_CTRL_EIC_IER_FMC1_TRIG            WBGEN2_GEN_MASK(2, 1)

/* definitions for field: FMC slot 2 end of acquisition interrupt in reg: Interrupt enable register */
#define IRQ_CTRL_EIC_IER_FMC1_ACQ_END         WBGEN2_GEN_MASK(3, 1)

/* definitions for register: Interrupt mask register */

/* definitions for field: FMC slot 1 trigger interrupt in reg: Interrupt mask register */
#define IRQ_CTRL_EIC_IMR_FMC0_TRIG            WBGEN2_GEN_MASK(0, 1)

/* definitions for field: FMC slot 1 end of acquisition interrupt in reg: Interrupt mask register */
#define IRQ_CTRL_EIC_IMR_FMC0_ACQ_END         WBGEN2_GEN_MASK(1, 1)

/* definitions for field: FMC slot 2 trigger interrupt in reg: Interrupt mask register */
#define IRQ_CTRL_EIC_IMR_FMC1_TRIG            WBGEN2_GEN_MASK(2, 1)

/* definitions for field: FMC slot 2 end of acquisition interrupt in reg: Interrupt mask register */
#define IRQ_CTRL_EIC_IMR_FMC1_ACQ_END         WBGEN2_GEN_MASK(3, 1)

/* definitions for register: Interrupt status register */

/* definitions for field: FMC slot 1 trigger interrupt in reg: Interrupt status register */
#define IRQ_CTRL_EIC_ISR_FMC0_TRIG            WBGEN2_GEN_MASK(0, 1)

/* definitions for field: FMC slot 1 end of acquisition interrupt in reg: Interrupt status register */
#define IRQ_CTRL_EIC_ISR_FMC0_ACQ_END         WBGEN2_GEN_MASK(1, 1)

/* definitions for field: FMC slot 2 trigger interrupt in reg: Interrupt status register */
#define IRQ_CTRL_EIC_ISR_FMC1_TRIG            WBGEN2_GEN_MASK(2, 1)

/* definitions for field: FMC slot 2 end of acquisition interrupt in reg: Interrupt status register */
#define IRQ_CTRL_EIC_ISR_FMC1_ACQ_END         WBGEN2_GEN_MASK(3, 1)

PACKED struct IRQ_CTRL_WB {
  /* [0x0]: REG Interrupt disable register */
  uint32_t EIC_IDR;
  /* [0x4]: REG Interrupt enable register */
  uint32_t EIC_IER;
  /* [0x8]: REG Interrupt mask register */
  uint32_t EIC_IMR;
  /* [0xc]: REG Interrupt status register */
  uint32_t EIC_ISR;
};

#endif
