Work in progress.

Add a few comments in fmc_adc module.

Add proper exception handling.
Add test time measurement.

Most of the function still needs to be tested.

Adding exception handling, updating interfaces to common modules.

fmcadc100m_csr register map is now in a separate file.
Add reserved fields in carrier_csr and irq_controller_regs.

Was badly concatenating the returned string.

UTC tag read is still to be modified.

This is in prevision of those files beeing automatically generated by wbgen2.

Test00 modified consequently.
Add test time measurement.

fmc_adc_spec.py contains a class to access carrier (SPEC in this case) specific features.
This module will replace spec_fmc_adc.py

Registers and register's fields are described in a dictionary.
This dictionary could later be generated by wbgen.
Generic functions allow to set/get registers or register's fields.
Another generic function prints the entire register map.

TODO:
 - Upgrade UTC and IRQ controller core with the register map dictionary.
 - Review DMA transfer functions.

test00 modified to use fpga loader library, csr module from common folder
and rr module from gnurabbit/python folder.

Fix C shared library path in rr.py
Remove undefined rr_read and rr_write from rrlib.h
Remove rr.py and rrlib.so from pts root directory.
Put updated versions of rr.py, rrlib.so and rr_loader_lib.so in
test/fmcadc100m14b4cha/python those should be removed when all
tests will use common modules.

Modify test04 to verify that Si570 output frequency is within the limits. Instead of just checking Si570 registers value, that might be different from chip to chip.