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FMC ADC 100M 14b 4cha - Testing
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FMC ADC 100M 14b 4cha - Testing
Commits
fea8c6d4
Commit
fea8c6d4
authored
Dec 06, 2013
by
Matthieu Cattin
Browse files
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Plain Diff
many: Change interrupt scheme, now uses two stages (eic + vic).
parent
5c7369f1
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Showing
19 changed files
with
319 additions
and
365 deletions
+319
-365
fmc_adc.py
test/fmcadc100m14b4cha/python/fmc_adc.py
+83
-3
fmc_adc_demo.py
test/fmcadc100m14b4cha/python/fmc_adc_demo.py
+3
-2
fmc_adc_spec.py
test/fmcadc100m14b4cha/python/fmc_adc_spec.py
+132
-282
test07.py
test/fmcadc100m14b4cha/python/test07.py
+5
-5
test08.py
test/fmcadc100m14b4cha/python/test08.py
+5
-5
test09.py
test/fmcadc100m14b4cha/python/test09.py
+4
-4
test11.py
test/fmcadc100m14b4cha/python/test11.py
+3
-1
test12.py
test/fmcadc100m14b4cha/python/test12.py
+4
-4
test15.py
test/fmcadc100m14b4cha/python/test15.py
+4
-4
test16.py
test/fmcadc100m14b4cha/python/test16.py
+4
-4
test17.py
test/fmcadc100m14b4cha/python/test17.py
+1
-1
test19.py
test/fmcadc100m14b4cha/python/test19.py
+4
-4
test20.py
test/fmcadc100m14b4cha/python/test20.py
+24
-9
test22.py
test/fmcadc100m14b4cha/python/test22.py
+4
-4
test25.py
test/fmcadc100m14b4cha/python/test25.py
+4
-4
test27.py
test/fmcadc100m14b4cha/python/test27.py
+3
-3
test28.py
test/fmcadc100m14b4cha/python/test28.py
+24
-18
test30.py
test/fmcadc100m14b4cha/python/test30.py
+4
-4
test32.py
test/fmcadc100m14b4cha/python/test32.py
+4
-4
No files found.
test/fmcadc100m14b4cha/python/fmc_adc.py
View file @
fea8c6d4
...
...
@@ -29,6 +29,7 @@ from si57x import *
# Import register maps
from
utc_core_regs
import
*
from
fmc_adc_eic_regs
import
*
from
fmcadc100m_csr
import
*
...
...
@@ -57,11 +58,12 @@ class FmcAdc100mOperationError(Exception):
class
CFmcAdc100m
:
UTC_CORE_ADDR
=
0x0
FMC_EIC_ADDR
=
0x0
UTC_CORE_ADDR
=
0x100
# FOR SVEC ONLY
DDR_DAT_ADDR
=
0x
01
00
DDR_ADR_ADDR
=
0x
0
200
DDR_DAT_ADDR
=
0x
10
00
DDR_ADR_ADDR
=
0x200
FMC_SYS_I2C_ADDR
=
0x1000
EEPROM_ADDR
=
0x50
...
...
@@ -115,6 +117,7 @@ class CFmcAdc100m:
try
:
# Objects declaration
self
.
fmc_eic
=
CCSR
(
self
.
bus
,
self
.
adc_mezz_offset
+
self
.
FMC_EIC_ADDR
,
FMC_ADC_EIC_REGS
)
self
.
utc_core
=
CCSR
(
self
.
bus
,
self
.
adc_mezz_offset
+
self
.
UTC_CORE_ADDR
,
UTC_CORE_REGS
)
self
.
fmc_sys_i2c
=
COpenCoresI2C
(
self
.
bus
,
self
.
adc_core_offset
+
self
.
FMC_SYS_I2C_ADDR
,
249
)
...
...
@@ -205,6 +208,83 @@ class CFmcAdc100m:
print
(
"Test pattern :
%.4
X"
)
%
self
.
adc_cfg
.
get_testpat
()
print
(
"Test pattern status :
%.1
X"
)
%
self
.
adc_cfg
.
get_testpat_stat
()
#======================================================================
# FMC-ADC Enhanced Interrupt Controller (EIC)
# Print FMC-ADC EIC register map
def
print_eic_regs
(
self
):
self
.
fmc_eic
.
print_reg_map
()
# Enable trigger interrupt
def
enable_trig_irq
(
self
):
try
:
self
.
fmc_eic
.
set_field
(
'IER'
,
'TRIG'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
# Disable trigger interrupt
def
disable_trig_irq
(
self
):
try
:
self
.
fmc_eic
.
set_field
(
'IDR'
,
'TRIG'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
# Clear trigger interrupt
def
clear_trig_irq
(
self
):
try
:
self
.
fmc_eic
.
set_field
(
'ISR'
,
'TRIG'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
# Enable acquisition end interrupt
def
enable_acq_end_irq
(
self
):
try
:
self
.
fmc_eic
.
set_field
(
'IER'
,
'ACQ_END'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
# Disable acquisition end interrupt
def
disable_acq_end_irq
(
self
):
try
:
self
.
fmc_eic
.
set_field
(
'IDR'
,
'ACQ_END'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
# Clear acquisition end interrupt
def
clear_acq_end_irq
(
self
):
try
:
self
.
fmc_eic
.
set_field
(
'ISR'
,
'ACQ_END'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
# Get FMC-ADC EIC enable mask
def
get_eic_en_mask
(
self
):
try
:
return
self
.
fmc_eic
.
get_reg
(
'IMR'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
# Get FMC-ADC interrupt source
def
get_eic_src
(
self
):
try
:
return
self
.
fmc_eic
.
get_reg
(
'ISR'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
# Get trigger interrupt status
def
get_trig_status
(
self
):
try
:
return
self
.
fmc_eic
.
get_field
(
'ISR'
,
'TRIG'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
# Get end of acq interrupt status
def
get_acq_end_status
(
self
):
try
:
return
self
.
fmc_eic
.
get_field
(
'ISR'
,
'ACQ_END'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
#======================================================================
# UTC core
...
...
test/fmcadc100m14b4cha/python/fmc_adc_demo.py
View file @
fea8c6d4
...
...
@@ -233,8 +233,9 @@ if __name__ == "__main__":
sine
=
SineWaveform
()
carrier
=
CFmcAdc100mSpec
(
spec
,
0x1
)
# Enable DMA interrupts (finished, error)
carrier
.
set_irq_en_mask
(
0x3
)
# Enable DMA interrupts
carrier
.
enable_dma_done_irq
()
carrier
.
enable_dma_error_irq
()
# Set UTC
current_time
=
time
.
time
()
...
...
test/fmcadc100m14b4cha/python/fmc_adc_spec.py
View file @
fea8c6d4
...
...
@@ -19,11 +19,11 @@ from csr import *
from
onewire
import
*
from
gn4124
import
*
from
ds18b20
import
*
from
vic
import
*
# Import register maps
from
spec_carrier_csr
import
*
from
spec_irq_controller_regs
import
*
from
utc_core_regs
import
*
from
dma_eic_regs
import
*
# Class to access fmcadc100m14b4cha SPEC specific Wishbone cores
...
...
@@ -40,8 +40,8 @@ class CFmcAdc100mSpec:
GNUM_DMA_CSR_ADDR
=
0x1000
ONEWIRE_ADDR
=
0x1100
CSR_ADDR
=
0x1200
UTC_CORE_ADDR
=
0x20
00
IRQ_CONTROLLER_ADDR
=
0x13
00
VIC_ADDR
=
0x13
00
GNUM_DMA_EIC_ADDR
=
0x14
00
# Onewire core port
DS18B20_PORT
=
0
...
...
@@ -53,12 +53,6 @@ class CFmcAdc100mSpec:
tag_stop
=
[
0x28
,
0
,
0
,
0
,
0
]
tag_end
=
[
0x38
,
0
,
0
,
0
,
0
]
# IRQ controller
IRQ_SRC_DMA_END
=
0x1
IRQ_SRC_DMA_ERR
=
0x2
IRQ_SRC_ACQ_TRG
=
0x4
IRQ_SRC_ACQ_END
=
0x8
# Gennum interface
DMA_LENGTH
=
4096
# DMA length in bytes
...
...
@@ -75,8 +69,8 @@ class CFmcAdc100mSpec:
self
.
onewire
=
COpenCoresOneWire
(
self
.
bus
,
self
.
ONEWIRE_ADDR
,
624
,
124
)
self
.
ds18b20
=
CDS18B20
(
self
.
onewire
,
self
.
DS18B20_PORT
)
self
.
csr
=
CCSR
(
self
.
bus
,
self
.
CSR_ADDR
,
CARRIER_CSR
)
self
.
utc_core
=
CCSR
(
self
.
bus
,
self
.
UTC_CORE_ADDR
,
UTC_CORE_REGS
)
self
.
irq_controller
=
CCSR
(
self
.
bus
,
self
.
IRQ_CONTROLLER_ADDR
,
IRQ_CONTROLLER
_REGS
)
self
.
vic
=
CVic
(
self
.
bus
,
self
.
VIC_ADDR
)
self
.
dma_eic
=
CCSR
(
self
.
bus
,
self
.
GNUM_DMA_EIC_ADDR
,
DMA_EIC
_REGS
)
# Get physical addresses of the pages for DMA transfer
self
.
dma_pages
=
self
.
gnum
.
get_physical_addr
()
...
...
@@ -89,6 +83,16 @@ class CFmcAdc100mSpec:
# Release the mezzanine software reset
self
.
set_sw_rst
(
1
)
# Configure VIC
#self.vic.print_regs()
self
.
vic
.
set_polarity
(
1
)
# output active high
self
.
vic
.
enable_emu_edge
(
750
)
# emulate edge sensitive output (pulse width = 750 * 1/sys_clk = 6us)
self
.
vic
.
enable_int
(
0
)
# enable interrupts from fmc0 eic
self
.
vic
.
enable_int
(
1
)
# enable interrupts from dma eic
self
.
vic
.
enable_module
()
self
.
fmc_eic_addr
=
self
.
vic
.
get_vector_addr
(
0
)
self
.
dma_eic_addr
=
self
.
vic
.
get_vector_addr
(
1
)
# TODO
# Check if the expected bitstream loaded
#bs = self.get_bitstream_type()
...
...
@@ -237,199 +241,94 @@ class CFmcAdc100mSpec:
#======================================================================
#
UTC core
#
Vectored Interrupt Controller (VIC)
#
Print UTC core register map
def
print_utc_core_regs
(
self
):
self
.
utc_core
.
print_reg_map
()
#
Get current interrupt vector address
def
vic_get_current_vector_addr
(
self
):
return
self
.
vic
.
get_int_vector_addr
()
# Set UTC core with current computer time
def
set_utc_time
(
self
):
try
:
current_time
=
time
.
time
()
utc_seconds
=
int
(
current_time
)
self
.
utc_core
.
set_reg
(
'SECONDS'
,
utc_seconds
)
utc_coarse
=
int
((
current_time
-
utc_seconds
)
/
8E-9
)
self
.
utc_core
.
set_reg
(
'COARSE'
,
utc_coarse
)
return
current_time
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
# Acknowledge current vector
def
vic_ack_current_vector
(
self
):
self
.
vic
.
int_ack
()
# Returns UTC seconds counter value
def
get_utc_second_cnt
(
self
):
try
:
return
self
.
utc_core
.
get_reg
(
'SECONDS'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
# Get raw interrupt status
def
vic_get_raw_status
(
self
):
return
self
.
vic
.
get_raw_int_status
()
# Set UTC seconds counter
def
set_utc_second_cnt
(
self
,
value
):
try
:
self
.
utc_core
.
set_reg
(
'SECONDS'
,
value
)
return
self
.
utc_core
.
get_reg
(
'SECONDS'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
#======================================================================
# DMA Enhanced Interrupt Controller (EIC)
# Returns UTC coarse counter value
def
get_utc_coarse_cnt
(
self
):
try
:
return
self
.
utc_core
.
get_reg
(
'COARSE'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
# Print DMA EIC register map
def
print_dma_eic_regs
(
self
):
self
.
dma_eic
.
print_reg_map
()
#
Set UTC coarse counter
def
set_utc_coarse_cnt
(
self
,
value
):
#
Enable DMA done interrupt
def
enable_dma_done_irq
(
self
):
try
:
self
.
utc_core
.
set_reg
(
'COARSE'
,
value
)
return
self
.
utc_core
.
get_reg
(
'COARSE'
)
self
.
dma_eic
.
set_field
(
'IER'
,
'DMA_END'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
###########################################################################
########## Code to review ##########
# Returns last trigger event time-tag
def
get_utc_trig_tag
(
self
):
# Get metadata
addr
=
self
.
tag_trig
[
0
]
self
.
tag_trig
[
1
]
=
self
.
utc_core
.
rd_reg
(
addr
)
# Get seconds
addr
=
self
.
tag_trig
[
0
]
+
0x4
self
.
tag_trig
[
2
]
=
self
.
utc_core
.
rd_reg
(
addr
)
# Get coarse
addr
=
self
.
tag_trig
[
0
]
+
0x8
self
.
tag_trig
[
3
]
=
self
.
utc_core
.
rd_reg
(
addr
)
# Get fine
addr
=
self
.
tag_trig
[
0
]
+
0xc
self
.
tag_trig
[
4
]
=
self
.
utc_core
.
rd_reg
(
addr
)
return
self
.
tag_trig
# Returns last acquisition start event time-tag
def
get_utc_start_tag
(
self
):
# Get metadata
addr
=
self
.
tag_start
[
0
]
self
.
tag_start
[
1
]
=
self
.
utc_core
.
rd_reg
(
addr
)
# Get seconds
addr
=
self
.
tag_start
[
0
]
+
0x4
self
.
tag_start
[
2
]
=
self
.
utc_core
.
rd_reg
(
addr
)
# Get coarse
addr
=
self
.
tag_start
[
0
]
+
0x8
self
.
tag_start
[
3
]
=
self
.
utc_core
.
rd_reg
(
addr
)
# Get fine
addr
=
self
.
tag_start
[
0
]
+
0xc
self
.
tag_start
[
4
]
=
self
.
utc_core
.
rd_reg
(
addr
)
return
self
.
tag_start
# Returns last acquisition stop event time-tag
def
get_utc_stop_tag
(
self
):
# Get metadata
addr
=
self
.
tag_stop
[
0
]
self
.
tag_stop
[
1
]
=
self
.
utc_core
.
rd_reg
(
addr
)
# Get seconds
addr
=
self
.
tag_stop
[
0
]
+
0x4
self
.
tag_stop
[
2
]
=
self
.
utc_core
.
rd_reg
(
addr
)
# Get coarse
addr
=
self
.
tag_stop
[
0
]
+
0x8
self
.
tag_stop
[
3
]
=
self
.
utc_core
.
rd_reg
(
addr
)
# Get fine
addr
=
self
.
tag_stop
[
0
]
+
0xc
self
.
tag_stop
[
4
]
=
self
.
utc_core
.
rd_reg
(
addr
)
return
self
.
tag_stop
# Returns last acquisition end event time-tag
def
get_utc_end_tag
(
self
):
# Get metadata
addr
=
self
.
tag_end
[
0
]
self
.
tag_end
[
1
]
=
self
.
utc_core
.
rd_reg
(
addr
)
# Get seconds
addr
=
self
.
tag_end
[
0
]
+
0x4
self
.
tag_end
[
2
]
=
self
.
utc_core
.
rd_reg
(
addr
)
# Get coarse
addr
=
self
.
tag_end
[
0
]
+
0x8
self
.
tag_end
[
3
]
=
self
.
utc_core
.
rd_reg
(
addr
)
# Get fine
addr
=
self
.
tag_end
[
0
]
+
0xc
self
.
tag_end
[
4
]
=
self
.
utc_core
.
rd_reg
(
addr
)
return
self
.
tag_end
###########################################################################
#======================================================================
# Interrupt controller core
# Print IRq controller register map
def
print_irq_controller_regs
(
self
):
self
.
irq_controller
.
print_reg_map
()
# Set IRQ enable mask
def
set_irq_en_mask
(
self
,
mask
):
# Disable DMA done interrupt
def
disable_dma_done_irq
(
self
):
try
:
self
.
irq_controller
.
set_reg
(
'EN_MASK'
,
mask
)
return
self
.
irq_controller
.
get_reg
(
'EN_MASK'
)
self
.
dma_eic
.
set_field
(
'IDR'
,
'DMA_END'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
#
Get IRQ enable mask
def
get_irq_en_mask
(
self
):
#
Clear DMA done interrupt
def
clear_dma_done_irq
(
self
):
try
:
return
self
.
irq_controller
.
get_reg
(
'EN_MASK'
)
self
.
dma_eic
.
set_field
(
'ISR'
,
'DMA_END'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
#
Returns multiple IRQ status
def
get_irq_mult
(
self
):
#
Enable DMA error interrupt
def
enable_dma_error_irq
(
self
):
try
:
return
self
.
irq_controller
.
get_reg
(
'MULTI_IRQ'
)
self
.
dma_eic
.
set_field
(
'IER'
,
'DMA_ERR'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
#
Clears multiple IRQ status
def
clear_irq_mult
(
self
,
irq
):
#
Disable DMA error interrupt
def
disable_dma_error_irq
(
self
):
try
:
self
.
irq_controller
.
set_reg
(
'MULTI_IRQ'
,
irq
)
return
self
.
irq_controller
.
get_reg
(
'MULTI_IRQ'
)
self
.
dma_eic
.
set_field
(
'IDR'
,
'DMA_ERR'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
#
Returns IRQ source
def
get_irq_source
(
self
):
#
Clear DMA error interrupt
def
clear_dma_error_irq
(
self
):
try
:
return
self
.
irq_controller
.
get_reg
(
'SRC'
)
self
.
dma_eic
.
set_field
(
'ISR'
,
'DMA_ERR'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
#
Clears IRQ source
def
clear_irq_source
(
self
,
irq
):
#
Get DMA EIC enable mask
def
get_dma_eic_en_mask
(
self
):
try
:
self
.
irq_controller
.
set_reg
(
'SRC'
,
irq
)
return
self
.
irq_controller
.
get_reg
(
'SRC'
)
return
self
.
dma_eic
.
get_reg
(
'IMR'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
#
Set dma done interrupt mask
def
set_irq_dma_done_mask
(
self
,
value
):
#
Get DMA EIC interrupt source
def
get_dma_eic_src
(
self
):
try
:
return
self
.
irq_controller
.
set_field
(
'EN_MASK'
,
'DMA_END'
,
value
)
return
self
.
dma_eic
.
get_reg
(
'ISR'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
#
Set acquisition end interrupt mask
def
set_irq_acq_end_mask
(
self
,
value
):
#
Get DMA done interrupt status
def
get_dma_done_status
(
self
):
try
:
return
self
.
irq_controller
.
set_field
(
'EN_MASK'
,
'ACQ_END'
,
value
)
return
self
.
dma_eic
.
get_field
(
'ISR'
,
'DMA_END'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
#
Set trigger interrupt mask
def
set_irq_trig_mask
(
self
,
value
):
#
Get DMA error interrupt status
def
get_dma_error_status
(
self
):
try
:
return
self
.
irq_controller
.
set_field
(
'EN_MASK'
,
'ACQ_TRG'
,
value
)
return
self
.
dma_eic
.
get_field
(
'ISR'
,
'DMA_ERR'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
...
...
@@ -441,17 +340,18 @@ class CFmcAdc100mSpec:
###########################################################################
########## Code to review ##########
#
Make a
DMA transfer
# carrier_addr
and length are in bytes
def
get_data
(
self
,
carrier_addr
,
length
):
# Configure DMA
#
Configure
DMA transfer
# carrier_addr
: dma start address on the carrier side (in bytes)
# length : dma total length (in bytes)
def
cfg_dma
(
self
,
carrier_addr
,
length
,
verbose
=
False
):
if
length
==
0
:
raise
Exception
(
'Cannot retreive data of zero length!'
)
items_required
=
int
(
math
.
ceil
(
length
/
float
(
self
.
DMA_LENGTH
)))
if
(
128
<
items_required
):
print
(
'Required items:
%
d'
)
%
items_required
raise
Exception
(
'Current gn4124 class only supports up to 128 items.'
)
#print('Required items: %d')%items_required
if
verbose
:
print
(
'Required items:
%
d'
)
%
items_required
for
num
in
range
(
items_required
):
if
(
items_required
==
num
+
1
):
next_item
=
0
...
...
@@ -463,120 +363,77 @@ class CFmcAdc100mSpec:
item_start_addr
=
carrier_addr
else
:
item_start_addr
=
carrier_addr
+
(
num
*
self
.
DMA_LENGTH
)
#print("item nb:%d item_carrier_addr:0x%.8X item_host_addr:0x%.8X item_length:%d next_item:%d)")%(num,item_start_addr,self.dma_pages[num+1],item_length,next_item)
if
verbose
:
print
(
"item nb:
%
d item_carrier_addr:0x
%.8
X item_host_addr:0x
%.8
X item_length:
%
d next_item:
%
d)"
)
%
(
num
,
item_start_addr
,
self
.
dma_pages
[
num
+
1
],
item_length
,
next_item
)
self
.
gnum
.
add_dma_item
(
item_start_addr
,
self
.
dma_pages
[
num
+
1
],
item_length
,
0
,
next_item
)
items
=
self
.
gnum
.
get_memory_page
(
0
)
return
items_required
#self.gnum.print_dma_items()
#print('DMA items:')
#for i in range(items_required*8):
# print('%.4X: %.8X')%(i*4,items[i])
#self.print_irq_controller_regs()
#time.sleep(3)
# Start DMA and wait for DMA DONE interrupt
def
make_dma
(
self
,
verbose
=
False
):
# Start DMA
self
.
gnum
.
start_dma
()
# Wait for end of DMA interrupt
#print('Wait GN4124 interrupt')
self
.
gnum
.
wait_irq
()
#print('GN4124 interrupt occured')
dma_finished
=
0
#self.print_irq_controller_regs()
#print('irq mask:%.4X')%self.get_irq_en_mask()
while
(
0
==
dma_finished
):
irq_src
=
self
.
get_irq_source
()
#print('IRQ source : %.4X')%irq_src
#print('DMA status: %s')%self.gnum.get_dma_status()
if
(
irq_src
&
self
.
IRQ_SRC_DMA_END
):
#print('IRQ source : %.4X')%irq_src
self
.
clear_irq_source
(
self
.
IRQ_SRC_DMA_END
)
#print('IRQ source : %.4X')%self.get_irq_source()
dma_finished
=
1
time
.
sleep
(
0.005
)
#print('DMA finished!')
if
verbose
:
print
(
"VIC enable mask: 0x
%08
X"
%
(
self
.
vic
.
get_int_enable_mask
()))
print
(
"DMA EIC enable mask: 0x
%08
X"
%
self
.
get_dma_eic_en_mask
())
self
.
gnum
.
wait_irq
(
verbose
)
# Check if interrupt is DMA DONE
if
verbose
:
print
(
'Check if interrupt is DMA_DONE'
)
irq_src
=
self
.
get_dma_eic_src
()
irq_vect
=
self
.
vic_get_current_vector_addr
()
if
verbose
:
print
(
"DMA EIC irq source :
%.8
X"
%
irq_src
)
print
(
"VIC current vector : 0x
%08
X"
%
irq_vect
)
if
(
irq_vect
==
self
.
dma_eic_addr
):
if
(
self
.
get_dma_done_status
()):
self
.
clear_dma_done_irq
()
self
.
vic_ack_current_vector
()
if
verbose
:
print
(
"DMA EIC irq source :
%.8
X"
%
self
.
get_dma_eic_src
())
else
:
raise
FmcAdc100mSpecOperationError
(
"Bad IRQ source : 0x
%08
X"
%
irq_src
)
else
:
raise
FmcAdc100mSpecOperationError
(
"Bad IRQ vector. expected:0x
%08
X got:0x
%08
X"
%
(
self
.
dma_eic_addr
,
irq_vect
))
if
verbose
:
print
(
'DMA finished!'
)
# Reads data from carrier's DDR memory
def
get_data
(
self
,
carrier_addr
,
length
,
verbose
=
False
):
# Configure DMA
items_required
=
self
.
cfg_dma
(
carrier_addr
,
length
,
verbose
)
# make DMA
self
.
make_dma
(
verbose
)
# Retrieve data from host memory
data
=
[]
for
i
in
range
(
items_required
):
data
+=
self
.
gnum
.
get_memory_page
(
i
+
1
)
#print('data length:%d')%(len(data)*4)
if
verbose
:
print
(
'data length:
%
d'
)
%
(
len
(
data
)
*
4
)
channels_data
=
[]
for
i
in
range
(
length
/
4
):
channels_data
.
append
(
data
[
i
]
&
0xFFFF
)
channels_data
.
append
(
data
[
i
]
>>
16
)
#print('channels data length:%d')%(len(channels_data))
if
verbose
:
print
(
'channels data length:
%
d'
)
%
(
len
(
channels_data
))
return
channels_data
# Wait end of acquisition
def
wait_end_acq
(
self
):
acq_end
=
0
while
(
0
==
acq_end
):
irq_src
=
self
.
get_irq_source
()
print
(
'IRQ source :
%.4
X'
)
%
irq_src
if
(
irq_src
&
self
.
IRQ_SRC_ACQ_END
):
self
.
clear_irq_source
(
self
.
IRQ_SRC_ACQ_END
)
print
(
'IRQ source :
%.4
X'
)
%
self
.
get_irq_source
()
acq_end
=
1
print
(
'ACQ finished!'
)
# Writes data pattern to carrier's DDR memory
def
put_data
(
self
,
carrier_addr
,
pattern
,
length
,
verbose
=
False
):
# Configure DMA
items_required
=
int
(
math
.
ceil
(
length
/
float
(
self
.
DMA_LENGTH
)))
if
(
128
<
items_required
):
print
(
'Required items:
%
d'
)
%
items_required
raise
Exception
(
'Current gn4124 class only supports up to 128 items.'
)
if
verbose
:
print
(
'Required items:
%
d'
)
%
items_required
for
num
in
range
(
items_required
):
if
(
items_required
==
num
+
1
):
next_item
=
0
item_length
=
(
length
-
(
num
*
self
.
DMA_LENGTH
))
else
:
next_item
=
1
item_length
=
self
.
DMA_LENGTH
if
(
0
==
num
):
item_start_addr
=
carrier_addr
else
:
item_start_addr
=
carrier_addr
+
(
num
*
self
.
DMA_LENGTH
)
#print("item nb:%d item_carrier_addr:0x%.8X item_host_addr:0x%.8X item_length:%d next_item:%d)")%(num,item_start_addr,self.dma_pages[num+1],item_length,next_item)
self
.
gnum
.
add_dma_item
(
item_start_addr
,
self
.
dma_pages
[
num
+
1
],
item_length
,
1
,
next_item
)
items
=
self
.
gnum
.
get_memory_page
(
0
)
#self.gnum.print_dma_items()
#print('DMA items:')
#for i in range(items_required*8):
# print('%.4X: %.8X')%(i*4,items[i])
self
.
cfg_dma
(
carrier_addr
,
length
,
verbose
)
# Write pattern to DMA reserved host memory pages
for
page
in
range
(
1
,
items_required
):
if
verbose
:
print
(
"Writting
%8
X pattern on host memory page
%
d"
%
(
pattern
,
page
))
self
.
gnum
.
set_memory_page
(
page
,
pattern
)
#self.print_irq_controller_regs()
#time.sleep(3)
# Start DMA
self
.
gnum
.
start_dma
()
# Wait for end of DMA interrupt
if
verbose
:
print
(
'Wait GN4124 interrupt'
)
self
.
gnum
.
wait_irq
()
if
verbose
:
print
(
'GN4124 interrupt occured'
)
dma_finished
=
0
if
verbose
:
#self.print_irq_controller_regs()
print
(
'irq mask:
%.4
X'
)
%
self
.
get_irq_en_mask
()
while
(
0
==
dma_finished
):
irq_src
=
self
.
get_irq_source
()
#print('IRQ source : %.4X')%irq_src
#print('DMA status: %s')%self.gnum.get_dma_status()
if
(
irq_src
&
self
.
IRQ_SRC_DMA_END
):
#print('IRQ source : %.4X')%irq_src
self
.
clear_irq_source
(
self
.
IRQ_SRC_DMA_END
)
#print('IRQ source : %.4X')%self.get_irq_source()
dma_finished
=
1
time
.
sleep
(
0.005
)
if
verbose
:
print
(
'DMA finished!'
)
# Make DMA
self
.
make_dma
(
verbose
)
# Writes pattern to entire carrier's DDR memory
def
clear_ddr
(
self
,
carrier_addr
,
pattern
,
length
,
verbose
=
False
):
...
...
@@ -586,7 +443,7 @@ class CFmcAdc100mSpec:
items_required
=
int
(
math
.
ceil
(
length
/
float
(
self
.
DMA_LENGTH
)))
if
(
128
*
255
<
items_required
):
print
(
'Required items:
%
d'
)
%
items_required
raise
Exception
(
'Current gn4124 class only supports up to
%
d items.'
%
(
128
*
255
))
raise
FmcAdc100mSpecOperationError
(
'Current gn4124 class only supports up to
%
d items.'
%
(
128
*
255
))
if
verbose
:
print
(
'Required items:
%
d'
)
%
items_required
for
num
in
range
(
items_required
):
...
...
@@ -602,38 +459,31 @@ class CFmcAdc100mSpec:
item_start_addr
=
carrier_addr
+
(
num
*
self
.
DMA_LENGTH
)
#print("item nb:%d item_carrier_addr:0x%.8X item_host_addr:0x%.8X item_length:%d next_item:%d)")%(num,item_start_addr,self.dma_pages[num+1],item_length,next_item)
self
.
gnum
.
add_dma_item
(
item_start_addr
,
self
.
dma_pages
[
-
1
],
item_length
,
1
,
next_item
)
#self.gnum.print_dma_items()
if
verbose
:
self
.
gnum
.
print_dma_items
()
# Write pattern to DMA reserved host memory page (last page)
self
.
gnum
.
set_memory_page
(
255
,
pattern
)
# Start DMA
self
.
gnum
.
start_dma
()
# Wait for end of DMA interrupt
if
verbose
:
print
(
'Wait GN4124 interrupt'
)
self
.
gnum
.
wait_irq
()
if
verbose
:
print
(
'GN4124 interrupt occured'
)
dma_finished
=
0
if
verbose
:
#self.print_irq_controller_regs()
print
(
"irq source :
%.8
X"
%
self
.
get_irq_source
())
print
(
'irq mask:
%.4
X'
)
%
self
.
get_irq_en_mask
()
# Make DMA
self
.
make_dma
(
verbose
)
while
(
0
==
dma_finished
):
#======================================================================
# Data acquisition
# Wait end of acquisition
def
wait_end_acq
(
self
):
acq_end
=
0
while
(
0
==
acq_end
):
irq_src
=
self
.
get_irq_source
()
if
verbose
:
print
(
'irq source (polling loop):
%.8
X'
)
%
irq_src
#print('DMA status: %s')%self.gnum.get_dma_status()
if
(
irq_src
&
self
.
IRQ_SRC_DMA_END
):
#print('IRQ source : %.4X')%irq_src
self
.
clear_irq_source
(
self
.
IRQ_SRC_DMA_END
)
if
verbose
:
print
(
"irq source :
%.8
X"
%
self
.
get_irq_source
())
dma_finished
=
1
time
.
sleep
(
0.005
)
if
verbose
:
print
(
'DMA finished!'
)
print
(
'IRQ source :
%.4
X'
)
%
irq_src
if
(
irq_src
&
self
.
IRQ_SRC_ACQ_END
):
self
.
clear_irq_source
(
self
.
IRQ_SRC_ACQ_END
)
print
(
'IRQ source :
%.4
X'
)
%
self
.
get_irq_source
()
acq_end
=
1
print
(
'ACQ finished!'
)
###########################################################################
test/fmcadc100m14b4cha/python/test07.py
View file @
fea8c6d4
...
...
@@ -93,12 +93,12 @@ def acq_channels(fmc, carrier):
return
1
# Retrieve data trough DMA
trig_pos
=
fmc
.
get_trig_pos
()
# Enable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x1
)
# Enable "DMA done" interrupt
carrier
.
enable_dma_done_irq
(
)
# Read ACQ_LENGTH samples after the trigger for all channels
channels_data
=
carrier
.
get_data
((
trig_pos
<<
3
),
ACQ_LENGTH
*
8
)
# Disable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x0
)
channels_data
=
carrier
.
get_data
((
trig_pos
<<
3
),
ACQ_LENGTH
*
8
,
False
)
# Disable "DMA done" interrupt
carrier
.
disable_dma_done_irq
(
)
channels_data
=
[
hex2signed
(
item
)
for
item
in
channels_data
]
return
channels_data
...
...
test/fmcadc100m14b4cha/python/test08.py
View file @
fea8c6d4
...
...
@@ -97,12 +97,12 @@ def get_channels_mean(fmc, carrier):
return
1
# Retrieve data trough DMA
trig_pos
=
fmc
.
get_trig_pos
()
# Enable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x1
)
# Enable "DMA done" interrupt
carrier
.
enable_dma_done_irq
(
)
# Read ACQ_LENGTH samples after the trigger for all channels
channels_data
=
carrier
.
get_data
((
trig_pos
<<
3
),
ACQ_LENGTH
*
8
)
# Disable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x0
)
channels_data
=
carrier
.
get_data
((
trig_pos
<<
3
),
ACQ_LENGTH
*
8
,
False
)
# Disable "DMA done" interrupt
carrier
.
disable_dma_done_irq
(
)
channels_data
=
[
hex2signed
(
item
)
for
item
in
channels_data
]
# calculate mean value for each channel
channels_mean
=
[]
...
...
test/fmcadc100m14b4cha/python/test09.py
View file @
fea8c6d4
...
...
@@ -141,12 +141,12 @@ def acq_channels(fmc, carrier):
return
1
# Retrieve data trough DMA
trig_pos
=
fmc
.
get_trig_pos
()
# Enable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x1
)
# Enable "DMA done" interrupt
carrier
.
enable_dma_done_irq
(
)
# Read ACQ_LENGTH samples after the trigger for all channels
channels_data
=
carrier
.
get_data
((
trig_pos
<<
3
),
ACQ_LENGTH
*
8
)
# Disable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x0
)
# Disable "DMA done" interrupt
carrier
.
disable_dma_done_irq
(
)
channels_data
=
[
hex2signed
(
item
)
for
item
in
channels_data
]
channels_data
=
[
digital2volt
(
item
,
1.0
,
16
)
for
item
in
channels_data
]
return
channels_data
...
...
test/fmcadc100m14b4cha/python/test11.py
View file @
fea8c6d4
...
...
@@ -171,7 +171,9 @@ def main (default_directory='.'):
sine
=
SineWaveform
()
# Enables DMA interrupts
print
(
'Set IRQ enable mask:
%.4
X'
)
%
spec_fmc
.
set_irq_en_mask
(
0x3
)
spec_fmc
.
enable_dma_done_irq
()
spec_fmc
.
enable_dma_error_irq
()
print
(
'Set IRQ enable mask:
%.4
X'
%
spec_fmc
.
get_dma_eic_en_mask
())
# Initialise fmc adc
fmc_adc_init
(
spec
,
fmc
)
...
...
test/fmcadc100m14b4cha/python/test12.py
View file @
fea8c6d4
...
...
@@ -104,12 +104,12 @@ def acq_channels(fmc, carrier, adc_fs, pause):
return
1
# Retrieve data trough DMA
trig_pos
=
fmc
.
get_trig_pos
()
# Enable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x1
)
# Enable "DMA done" interrupt
carrier
.
enable_dma_done_irq
(
)
# Read ACQ_LENGTH samples after the trigger for all channels
channels_data
=
carrier
.
get_data
((
trig_pos
<<
3
),
ACQ_LENGTH
*
8
)
# Disable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x0
)
# Disable "DMA done" interrupt
carrier
.
disable_dma_done_irq
(
)
channels_data
=
[
hex2signed
(
item
)
for
item
in
channels_data
]
channels_data
=
[
digital2volt
(
item
,
adc_fs
,
16
)
for
item
in
channels_data
]
return
channels_data
...
...
test/fmcadc100m14b4cha/python/test15.py
View file @
fea8c6d4
...
...
@@ -146,12 +146,12 @@ def acq_get_data(spec_fmc, fmc, adc_fs, adc_nbits=16):
return
1
# Retrieve data trough DMA
trig_pos
=
fmc
.
get_trig_pos
()
# Enable "DMA done" i
i
nterrupt
spec_fmc
.
set_irq_en_mask
(
0x1
)
# Enable "DMA done" interrupt
spec_fmc
.
enable_dma_done_irq
(
)
# Read ACQ_LENGTH samples after the trigger for all channels
channels_data
=
spec_fmc
.
get_data
((
trig_pos
<<
3
),
ACQ_LENGTH
*
8
)
# Disable "DMA done" i
i
nterrupt
spec_fmc
.
set_irq_en_mask
(
0x0
)
# Disable "DMA done" interrupt
spec_fmc
.
disable_dma_done_irq
(
)
channels_data
=
[
hex2signed
(
item
)
for
item
in
channels_data
]
channels_data
=
[
digital2volt
(
item
,
adc_fs
,
adc_nbits
)
for
item
in
channels_data
]
return
channels_data
...
...
test/fmcadc100m14b4cha/python/test16.py
View file @
fea8c6d4
...
...
@@ -117,12 +117,12 @@ def acq_channels(fmc, spec_fmc):
return
1
# Retrieve data trough DMA
trig_pos
=
fmc
.
get_trig_pos
()
# Enable "DMA done" i
i
nterrupt
spec_fmc
.
set_irq_en_mask
(
0x1
)
# Enable "DMA done" interrupt
spec_fmc
.
enable_dma_done_irq
(
)
# Read ACQ_LENGTH samples after the trigger for all channels
channels_data
=
spec_fmc
.
get_data
((
trig_pos
<<
3
),
ACQ_LENGTH
*
8
)
# Disable "DMA done" i
i
nterrupt
spec_fmc
.
set_irq_en_mask
(
0x0
)
# Disable "DMA done" interrupt
spec_fmc
.
disable_dma_done_irq
(
)
channels_data
=
[
hex2signed
(
item
)
for
item
in
channels_data
]
return
channels_data
...
...
test/fmcadc100m14b4cha/python/test17.py
View file @
fea8c6d4
...
...
@@ -216,7 +216,7 @@ def main (default_directory = '.'):
print
"GN4124 local bus freq: "
,
carrier
.
gnum
.
get_local_bus_freq
()
# Enable "DMA finished" IRQ
carrier
.
set_irq_en_mask
(
0x1
)
carrier
.
enable_dma_done_irq
(
)
# Initialise fmc adc
fmc_adc_init
(
spec
,
fmc
)
...
...
test/fmcadc100m14b4cha/python/test19.py
View file @
fea8c6d4
...
...
@@ -191,12 +191,12 @@ def acq_channel(carrier, fmc, ch, adc_fs, adc_nbits=16, pause=0.01):
return
1
# Retrieve data trough DMA
trig_pos
=
fmc
.
get_trig_pos
()
# Enable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x1
)
# Enable "DMA done" interrupt
carrier
.
enable_dma_done_irq
(
)
# Read ACQ_LENGTH samples after the trigger for all channels
channels_data
=
carrier
.
get_data
((
trig_pos
<<
3
),
ACQ_LENGTH
*
8
)
# Disable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x0
)
# Disable "DMA done" interrupt
carrier
.
disable_dma_done_irq
(
)
channels_data
=
[
hex2signed
(
item
)
for
item
in
channels_data
]
channels_data
=
[
digital2volt
(
item
,
adc_fs
,
adc_nbits
)
for
item
in
channels_data
]
#plot_all(channels_data, [mean(channels_data[0::4]),mean(channels_data[1::4]),mean(channels_data[2::4]),mean(channels_data[3::4])], 0.1)
...
...
test/fmcadc100m14b4cha/python/test20.py
View file @
fea8c6d4
...
...
@@ -165,12 +165,12 @@ def acq_channel(carrier, fmc, ch, adc_fs, adc_nbits=16, pause=0.01):
return
1
# Retrieve data trough DMA
trig_pos
=
fmc
.
get_trig_pos
()
# Enable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x1
)
# Enable "DMA done" interrupt
carrier
.
enable_dma_done_irq
(
)
# Read ACQ_LENGTH samples after the trigger for all channels
channels_data
=
carrier
.
get_data
((
trig_pos
<<
3
),
ACQ_LENGTH
*
8
)
# Disable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x0
)
# Disable "DMA done" interrupt
carrier
.
disable_dma_done_irq
(
)
channels_data
=
[
hex2signed
(
item
)
for
item
in
channels_data
]
channels_data
=
[
digital2volt_without_offset
(
item
,
adc_fs
,
adc_nbits
)
for
item
in
channels_data
]
channel_data
=
channels_data
[
ch
-
1
::
4
]
...
...
@@ -241,7 +241,11 @@ def main (default_directory = '.'):
AWG_BAUD
=
57600
CALIBR_FILENAME
=
"calibration_data.txt"
CALIBR_FILENAME
=
os
.
path
.
join
(
default_directory
,
CALIBR_FILENAME
)
CALIBR_BIN_FILENAME
=
"calibration_data.bin"
CALIBR_BIN_FILENAME
=
os
.
path
.
join
(
default_directory
,
CALIBR_BIN_FILENAME
)
EEPROM_BIN_FILENAME
=
"eeprom_content.out"
EEPROM_BIN_FILENAME
=
os
.
path
.
join
(
default_directory
,
EEPROM_BIN_FILENAME
)
EEPROM_SIZE
=
8192
# in Bytes
...
...
@@ -337,14 +341,25 @@ def main (default_directory = '.'):
f_eeprom
.
close
()
# Get calibration data
print
"Get calibration data from EEPROM."
eeprom_data
=
open
(
EEPROM_BIN_FILENAME
,
"rb"
)
.
read
()
int_use_data
=
ipmi_get_internal_use_data
(
eeprom_data
)
#print("Extract calibration binary file to: %s"%(CALIBR_BIN_FILENAME))
cmd
=
'sdb-read -e 0x200 '
+
EEPROM_BIN_FILENAME
+
' calib > '
+
CALIBR_BIN_FILENAME
print
(
"Exctract calibration binary file, cmd:
%
s"
%
(
cmd
))
os
.
system
(
cmd
)
print
"Get calibration data from binary file."
calibr_data
=
[]
f_calibr_data
=
open
(
CALIBR_BIN_FILENAME
,
"rb"
)
try
:
byte
=
f_calibr_data
.
read
(
1
)
while
byte
!=
""
:
calibr_data
.
append
(
ord
(
byte
))
byte
=
f_calibr_data
.
read
(
1
)
finally
:
f_eeprom
.
close
()
# Re-arrange correction data into 16-bit number (from bytes)
eeprom_corr_data
=
[]
for
i
in
range
(
0
,
len
(
int_use
_data
),
2
):
eeprom_corr_data
.
append
((
int_use_data
[
i
+
1
]
<<
8
)
+
(
int_use
_data
[
i
]))
for
i
in
range
(
0
,
len
(
calibr
_data
),
2
):
eeprom_corr_data
.
append
((
calibr_data
[
i
+
1
]
<<
8
)
+
(
calibr
_data
[
i
]))
print
"0x
%04
X"
%
eeprom_corr_data
[
-
1
]
print
"Calibration data length (16-bit):
%
d"
%
len
(
eeprom_corr_data
)
print
"Correction data from eeprom:"
...
...
test/fmcadc100m14b4cha/python/test22.py
View file @
fea8c6d4
...
...
@@ -91,12 +91,12 @@ def acq_channels(fmc, carrier):
return
1
# Retrieve data trough DMA
trig_pos
=
fmc
.
get_trig_pos
()
# Enable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x1
)
# Enable "DMA done" interrupt
carrier
.
enable_dma_done_irq
(
)
# Read ACQ_LENGTH samples after the trigger for all channels
channels_data
=
carrier
.
get_data
((
trig_pos
<<
3
),
ACQ_LENGTH
*
8
)
# Disable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x0
)
# Disable "DMA done" interrupt
carrier
.
disable_dma_done_irq
(
)
return
0
def
print_temp
(
temp
):
...
...
test/fmcadc100m14b4cha/python/test25.py
View file @
fea8c6d4
...
...
@@ -174,12 +174,12 @@ def acq_channel(carrier, fmc, ch, adc_fs, adc_nbits=16, pause=0.01):
return
1
# Retrieve data trough DMA
trig_pos
=
fmc
.
get_trig_pos
()
# Enable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x1
)
# Enable "DMA done" interrupt
carrier
.
enable_dma_done_irq
(
)
# Read ACQ_LENGTH samples after the trigger for all channels
channels_data
=
carrier
.
get_data
((
trig_pos
<<
3
),
ACQ_LENGTH
*
8
)
# Disable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x0
)
# Disable "DMA done" interrupt
carrier
.
disable_dma_done_irq
(
)
channels_data
=
[
hex2signed
(
item
)
for
item
in
channels_data
]
channels_data
=
[
digital2volt_without_offset
(
item
,
adc_fs
,
adc_nbits
)
for
item
in
channels_data
]
channel_data
=
channels_data
[
ch
-
1
::
4
]
...
...
test/fmcadc100m14b4cha/python/test27.py
View file @
fea8c6d4
...
...
@@ -95,7 +95,7 @@ def acq_channels(fmc, carrier):
print
(
"Trigger position: 0x
%8
X"
%
trig_pos
)
#carrier.print_irq_controller_regs()
# Enable "DMA done" interrupt
carrier
.
set_irq_en_mask
(
0x1
)
carrier
.
enable_dma_done_irq
(
)
#carrier.print_irq_controller_regs()
raw_input
(
"hit any key to start dma."
)
# Read ACQ_LENGTH samples after the trigger for all channels
...
...
@@ -103,8 +103,8 @@ def acq_channels(fmc, carrier):
channels_data
=
carrier
.
get_data
(
0
,
ACQ_LENGTH
*
8
)
#for carrier_addr in range(0,10*4096, 4096):
# channels_data = carrier.get_data(carrier_addr, 0x1000)
# Disable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x0
)
# Disable "DMA done" interrupt
carrier
.
disable_dma_done_irq
(
)
channels_data
=
[
hex2signed
(
item
)
for
item
in
channels_data
]
return
channels_data
...
...
test/fmcadc100m14b4cha/python/test28.py
View file @
fea8c6d4
...
...
@@ -156,7 +156,7 @@ def clear_ddr(carrier, verbose=False):
pattern
=
0x0
length
=
2
**
27
-
(
128
*
4096
)
# Enable "DMA done" interrupt
carrier
.
set_irq_dma_done_mask
(
1
)
carrier
.
enable_dma_done_irq
(
)
#carrier.print_irq_controller_regs()
# Test number of dma transfer required (max dma size limitation of gnurabbit driver)
dma_required
=
int
(
math
.
ceil
((
MEMORY_SIZE
<<
3
)
/
float
(
254
*
DMA_ITEM_SIZE
*
DMA_MAX_ITEMS
)))
...
...
@@ -176,7 +176,7 @@ def clear_ddr(carrier, verbose=False):
# Incerment dma start address
start_byte_addr
+=
dma_length
# Disable "DMA done" interrupt
carrier
.
set_irq_dma_done_mask
(
0
)
carrier
.
disable_dma_done_irq
(
)
# Returns calibration data from fmc eeprom
...
...
@@ -206,7 +206,7 @@ def get_calibr_data(fmc, eeprom_bin_filename, calibr_bin_filename, verbose=False
# Get calibration data
#print("Extract calibration binary file to: %s"%(CALIBR_BIN_FILENAME))
cmd
=
'sdb-read -e 0x
1000 '
+
eeprom_bin_filename
+
' calibration.sd
b > '
+
calibr_bin_filename
cmd
=
'sdb-read -e 0x
200 '
+
eeprom_bin_filename
+
' cali
b > '
+
calibr_bin_filename
if
verbose
:
print
(
"Exctract calibration binary file, cmd:
%
s"
%
(
cmd
))
os
.
system
(
cmd
)
...
...
@@ -333,11 +333,11 @@ def make_acq(carrier, fmc, verbose=False):
# Make sure no acquisition is running
fmc
.
stop_acq
()
# Enables acquisition end interrupt
carrier
.
set_irq_acq_end_mask
(
1
)
#
carrier.set_irq_trig_mask(1
)
fmc
.
enable_acq_end_irq
(
)
#
fmc.enable_trig_irq(
)
if
verbose
:
print
(
"IRQ mask
:
%.8
X"
%
carrier
.
get_irq
_en_mask
())
print
(
"IRQ source :
%.8
X"
%
carrier
.
get_irq_source
())
print
(
"IRQ mask
:
%.8
X"
%
fmc
.
get_eic
_en_mask
())
print
(
"IRQ source :
%.8
X"
%
fmc
.
get_eic_src
())
# Start acquisition
if
verbose
:
print
(
"Starting acquisition..."
)
...
...
@@ -352,20 +352,26 @@ def make_acq(carrier, fmc, verbose=False):
###########################
# Wait for trigger interrupt
#carrier.gnum.wait_irq
(
)
#carrier.gnum.wait_irq)
# Wait for acquisition end interrupt
carrier
.
gnum
.
wait_irq
()
irq_src
=
carrier
.
get_irq_source
()
irq_src
=
fmc
.
get_eic_src
()
irq_vect
=
carrier
.
vic_get_current_vector_addr
()
if
verbose
:
print
(
"IRQ source :
%.8
X"
%
irq_src
)
if
(
irq_src
&
carrier
.
IRQ_SRC_ACQ_END
):
carrier
.
clear_irq_source
(
carrier
.
IRQ_SRC_ACQ_END
)
if
verbose
:
print
(
"IRQ source :
%.8
X"
%
carrier
.
get_irq_source
())
print
(
"FMC EIC irq source :
%.8
X"
%
irq_src
)
print
(
"VIC current vector : 0x
%08
X"
%
irq_vect
)
if
(
irq_vect
==
carrier
.
fmc_eic_addr
):
if
(
fmc
.
get_acq_end_status
()):
fmc
.
clear_acq_end_irq
()
carrier
.
vic_ack_current_vector
()
if
verbose
:
print
(
"IRQ source : 0x
%08
X"
%
fmc
.
get_eic_src
())
else
:
raise
PtsError
(
"Bad IRQ source."
)
else
:
raise
PtsError
(
"Bad IRQ
source. expected:0x08 got:0x
%02
X"
%
(
irq_src
))
raise
PtsError
(
"Bad IRQ
vector. expected:0x
%08
X got:0x
%08
X"
%
(
carrier
.
fmc_eic_addr
,
irq_vect
))
if
'IDLE'
!=
fmc
.
get_acq_fsm_state
():
raise
PtsError
(
"Acq FSM not IDLE. Current state:
%
s"
%
fmc
.
get_acq_fsm_state
())
...
...
@@ -374,13 +380,13 @@ def make_acq(carrier, fmc, verbose=False):
print
(
"Acquisition finished."
)
# Disables acquisition end interrupt
carrier
.
set_irq_acq_end_mask
(
0
)
fmc
.
disable_acq_end_irq
(
)
# Make a linked list dma
def
make_dma
(
carrier
,
start_byte_addr
,
length_bytes
,
in_range
,
verbose
=
False
):
# Enable "DMA done" interrupt
carrier
.
set_irq_dma_done_mask
(
1
)
carrier
.
enable_dma_done_irq
(
)
#carrier.print_irq_controller_regs()
# Test number of dma transfer required (max dma size limitation of gnurabbit driver)
dma_required
=
int
(
math
.
ceil
(
length_bytes
/
float
(
DMA_ITEM_SIZE
*
DMA_MAX_ITEMS
)))
...
...
@@ -402,7 +408,7 @@ def make_dma(carrier, start_byte_addr, length_bytes, in_range, verbose=False):
# Incerment dma start address
start_byte_addr
+=
dma_length
# Disable "DMA done" interrupt
carrier
.
set_irq_dma_done_mask
(
0
)
carrier
.
disable_dma_done_irq
(
)
#carrier.print_irq_controller_regs()
return
data
...
...
test/fmcadc100m14b4cha/python/test30.py
View file @
fea8c6d4
...
...
@@ -103,12 +103,12 @@ def acq_channels(fmc, carrier, adc_fs, pause):
return
1
# Retrieve data trough DMA
trig_pos
=
fmc
.
get_trig_pos
()
# Enable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x1
)
# Enable "DMA done" interrupt
carrier
.
enable_dma_done_irq
(
)
# Read ACQ_LENGTH samples after the trigger for all channels
channels_data
=
carrier
.
get_data
((
trig_pos
<<
3
),
ACQ_LENGTH
*
8
)
# Disable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x0
)
# Disable "DMA done" interrupt
carrier
.
disable_dma_done_irq
(
)
channels_data
=
[
hex2signed
(
item
)
for
item
in
channels_data
]
channels_data
=
[
digital2volt
(
item
,
adc_fs
,
16
)
for
item
in
channels_data
]
return
channels_data
...
...
test/fmcadc100m14b4cha/python/test32.py
View file @
fea8c6d4
...
...
@@ -114,12 +114,12 @@ def acq_channels(fmc, carrier, adc_fs, pause):
return
1
# Retrieve data trough DMA
trig_pos
=
fmc
.
get_trig_pos
()
# Enable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x1
)
# Enable "DMA done" interrupt
carrier
.
enable_dma_done_irq
(
)
# Read ACQ_LENGTH samples after the trigger for all channels
channels_data
=
carrier
.
get_data
((
trig_pos
<<
3
),
ACQ_LENGTH
*
8
)
# Disable "DMA done" i
i
nterrupt
carrier
.
set_irq_en_mask
(
0x0
)
# Disable "DMA done" interrupt
carrier
.
disable_dma_done_irq
(
)
channels_data
=
[
hex2signed
(
item
)
for
item
in
channels_data
]
channels_data
=
[
digital2volt
(
item
,
adc_fs
,
16
)
for
item
in
channels_data
]
return
channels_data
...
...
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