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FMC ADC 100M 14b 4cha - Testing
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FMC ADC 100M 14b 4cha - Testing
Commits
f2682689
Commit
f2682689
authored
Dec 08, 2011
by
Matthieu Cattin
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Add test17, board calibration.
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test17.py
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#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2011
# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
import
sys
import
rr
import
time
import
os
from
numpy
import
*
from
pylab
import
*
from
ptsexcept
import
*
import
gn4124
import
spec_fmc_adc
import
fmc_adc
import
calibr_box
from
PAGE.Agilent33250A
import
*
from
PAGE.SineWaveform
import
*
"""
test17: Calibration
Note: Requires test00.py to run first to load the firmware!
"""
GN4124_CSR
=
0x0
USB_DEVICE
=
"/dev/ttyUSB0"
RS232_BAUD
=
57600
NB_CHANNELS
=
4
AWG_SET_SLEEP
=
1
SSR_SET_SLEEP
=
0.05
BOX_SET_SLEEP
=
0.5
DAC_SET_SLEEP
=
0.5
ACQ_TIMEOUT
=
10
MAX_FIRMWARE_RELOAD
=
10
PRE_TRIG_SAMPLES
=
10
POST_TRIG_SAMPLES
=
1000
NB_SHOTS
=
1
ACQ_LENGTH
=
512
# in samples
DMA_LENGTH
=
4096
# in bytes
def
load_firmware
(
default_directory
):
print
(
'Load firmware to FPGA'
)
path_fpga_loader
=
'../../../gnurabbit/user/fpga_loader'
;
path_firmware
=
'../firmwares/spec_fmcadc100m14b4cha_test.bin'
;
firmware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_firmware
)
print
firmware_loader
+
' '
+
bitstream
os
.
system
(
firmware_loader
+
' '
+
bitstream
)
time
.
sleep
(
2
);
def
disconnect_channels
(
fmc
):
for
i
in
range
(
1
,
NB_CHANNELS
+
1
):
fmc
.
set_input_range
(
i
,
'OPEN'
)
time
.
sleep
(
SSR_SET_SLEEP
)
def
fmc_adc_init
(
spec
,
fmc
):
print
(
'Initialise FMC board.'
)
fmc
.
__init__
(
spec
)
# Reset offset DACs
fmc
.
dc_offset_reset
()
# Make sure all switches are OFF
disconnect_channels
(
fmc
)
# Set trigger
fmc
.
set_soft_trig
()
# Set acquisition
fmc
.
set_pre_trig_samples
(
PRE_TRIG_SAMPLES
)
fmc
.
set_post_trig_samples
(
POST_TRIG_SAMPLES
)
fmc
.
set_shots
(
NB_SHOTS
)
# Print configuration
#fmc.print_adc_core_config()
def
set_awg_freq
(
gen
,
sine
,
freq
):
sine
.
frequency
=
freq
gen
.
play
(
sine
)
print
(
'Sine frequency:
%3.3
fMHz'
)
%
(
sine
.
frequency
/
1E6
)
time
.
sleep
(
AWG_SET_SLEEP
)
def
acquisition
(
fmc
,
spec_fmc
,
channel_nb
):
# Make sure no acquisition is running
fmc
.
stop_acq
()
#print('Acquisition FSM state : %s') % fmc.get_acq_fsm_state()
# Start acquisition
fmc
.
start_acq
()
time
.
sleep
(
0.01
)
# Trigger
fmc
.
sw_trig
()
# Wait end of acquisition
timeout
=
0
while
(
'IDLE'
!=
fmc
.
get_acq_fsm_state
()):
#print fmc.get_acq_fsm_state()
time
.
sleep
(
.1
)
timeout
+=
1
if
(
ACQ_TIMEOUT
<
timeout
):
print
(
'Acquisition timeout. Check that the AWG is switched ON and properly connected.'
)
return
1
# Retrieve data trough DMA
channels_data
=
spec_fmc
.
get_data
(
0x0
,
ACQ_LENGTH
*
8
)
return
channels_data
[
channel_nb
-
1
::
4
]
# Converts digital value to volts
def
digital2volt
(
value
,
full_scale
,
nb_bit
):
return
float
(
value
)
*
float
(
full_scale
)
/
2
**
nb_bit
-
full_scale
/
2.0
# Converts volts to digital value
def
volt2digital
(
value
,
full_scale
,
nb_bit
):
digital
=
(
value
+
full_scale
/
2
)
*
2
**
nb_bit
/
full_scale
if
(
digital
>
2
**
nb_bit
-
1
):
digital
=
2
**
nb_bit
-
1
if
(
digital
<
0
):
digital
=
0
return
int
(
digital
)
def
main
(
default_directory
=
'.'
):
# Load firmware to FPGA
load_firmware
(
default_directory
)
# Objects declaration
spec
=
rr
.
Gennum
()
# bind to the SPEC board
gnum
=
gn4124
.
CGN4124
(
spec
,
GN4124_CSR
)
spec_fmc
=
spec_fmc_adc
.
CSpecFmcAdc100Ms
(
spec
)
fmc
=
fmc_adc
.
CFmcAdc100Ms
(
spec
)
gen
=
Agilent33250A
(
device
=
USB_DEVICE
,
bauds
=
RS232_BAUD
)
sine
=
SineWaveform
()
box
=
calibr_box
.
CCalibr_box
(
1
)
# Enable "DMA finished" IRQ
spec_fmc
.
set_irq_en_mask
(
0x1
)
# Initialise fmc adc
fmc_adc_init
(
spec
,
fmc
)
# Disconnect all inputs
disconnect_channels
(
fmc
)
# Connect to AWG
gen
.
connect
()
gen
.
output
=
False
#
for
i
in
range
(
1
,
NB_CHANNELS
+
1
):
print
(
'
\n
Channel
%
d 10V range calibration'
)
%
i
print
(
'Measurment 1: channel input = 0V, offset DAC = 0V'
)
# Channel input to 0V
fmc
.
set_input_range
(
i
,
'10V'
)
fmc
.
set_input_term
(
i
,
'ON'
)
box
.
select_output
(
'AWG'
)
time
.
sleep
(
BOX_SET_SLEEP
)
# Offset DAC to 0V
dac_fs
=
10
# DAC full scale range is 10V
dac_nbits
=
16
dac_v
=
0.0
dac_d
=
volt2digital
(
dac_v
,
dac_fs
,
dac_nbits
)
print
(
'DAC value: 0x
%
X (
%
fV)'
)
%
(
dac_d
,
dac_v
)
fmc
.
set_dc_offset
(
i
,
dac_d
)
time
.
sleep
(
DAC_SET_SLEEP
)
# Acquire ADC data and average it
acq
=
acquisition
(
fmc
,
spec_fmc
,
i
)
adc_d
=
mean
(
acq
)
adc_nbits
=
16
adc_fs
=
10
adc_v
=
digital2volt
(
adc_d
,
adc_fs
,
adc_nbits
)
print
(
'adc_v=
%
fV adc_d=0x
%
X'
)
%
(
adc_v
,
adc_d
)
print
(
'Measurment 2: channel input = Vref, offset DAC = 0V'
)
# Channel input to Vref (~4.096V)
fmc
.
set_input_range
(
i
,
'10V'
)
fmc
.
set_input_term
(
i
,
'OFF'
)
box
.
select_output
(
'10V'
)
time
.
sleep
(
BOX_SET_SLEEP
)
# Acquire ADC data and average it
acq
=
acquisition
(
fmc
,
spec_fmc
,
i
)
adc_d
=
mean
(
acq
)
adc_nbits
=
16
adc_fs
=
10
adc_v
=
digital2volt
(
adc_d
,
adc_fs
,
adc_nbits
)
print
(
'adc_v=
%
fV adc_d=0x
%
X'
)
%
(
adc_v
,
adc_d
)
print
(
'Measurment 3: channel input = Vref, offset DAC = Vref'
)
# Offset DAC to Vref
dac_fs
=
10
# DAC full scale range is 10V
dac_nbits
=
16
dac_v
=
4.096
dac_d
=
volt2digital
(
dac_v
,
dac_fs
,
dac_nbits
)
print
(
'DAC value: 0x
%
X (
%
fV)'
)
%
(
dac_d
,
dac_v
)
fmc
.
set_dc_offset
(
i
,
dac_d
)
time
.
sleep
(
DAC_SET_SLEEP
)
# Acquire ADC data and average it
acq
=
acquisition
(
fmc
,
spec_fmc
,
i
)
adc_d
=
mean
(
acq
)
adc_nbits
=
16
adc_fs
=
10
adc_v
=
digital2volt
(
adc_d
,
adc_fs
,
adc_nbits
)
print
(
'adc_v=
%
fV adc_d=0x
%
X'
)
%
(
adc_v
,
adc_d
)
print
(
'Measurment 4: channel input = 0V, offset DAC = Vref'
)
# Channel input to 0V
fmc
.
set_input_range
(
i
,
'10V'
)
fmc
.
set_input_term
(
i
,
'ON'
)
box
.
select_output
(
'AWG'
)
time
.
sleep
(
BOX_SET_SLEEP
)
# Acquire ADC data and average it
acq
=
acquisition
(
fmc
,
spec_fmc
,
i
)
adc_d
=
mean
(
acq
)
adc_nbits
=
16
adc_fs
=
10
adc_v
=
digital2volt
(
adc_d
,
adc_fs
,
adc_nbits
)
print
(
'adc_v=
%
fV adc_d=0x
%
X'
)
%
(
adc_v
,
adc_d
)
# Disconnect channel input
fmc
.
set_input_range
(
i
,
'OPEN'
)
time
.
sleep
(
SSR_SET_SLEEP
)
"""
# Configure channel and box for 1V range
fmc.set_input_range(i, '1V')
box.select_output('1V')
time.sleep(SSR_SET_SLEEP)
# Configure channel and box for 100mV range
fmc.set_input_range(i, '100mV')
box.select_output('100mV')
time.sleep(SSR_SET_SLEEP)
# Disconnect channel input
fmc.set_input_range(i, 'OPEN')
time.sleep(SSR_SET_SLEEP)
"""
gen
.
close
()
# Check if an error occured during frequency response test
#if(error != 0):
# raise PtsError('An error occured during frequency response test, check log for details.')
if
__name__
==
'__main__'
:
main
()
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