Commit eeb2ea75 authored by Matthieu Cattin's avatar Matthieu Cattin

test38: Add test for un-mapped wishbone addresses.

parent 38d3e13f
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2011
# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 10/5/2012
# Import system modules
import sys
import time
import os
# Add common modules and libraries location to path
sys.path.append('../../../')
sys.path.append('../../../gnurabbit/python/')
sys.path.append('../../../common/')
# Import common modules
from ptsexcept import *
import rr
# Import specific modules
from fmc_adc_spec import *
"""
test38: Load firmware, try to access to an un-mapped wishbone address -> the host shouldn't hang!
"""
def main (default_directory='.'):
# Constants declaration
TEST_NB = 38
#FMC_ADC_ADDR = '1a39:0004/1a39:0004@000B:0000'
#FMC_ADC_BITSTREAM = '../firmwares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM = '../firmwares/spec_fmcadc100m14b4cha_test.bin'
FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM)
EXPECTED_BITSTREAM_TYPE = 0x1
start_test_time = time.time()
print "\n================================================================================"
print "==> Test%02d start\n" % TEST_NB
# SPEC object declaration
print "Loading hardware access library and opening device.\n"
spec = rr.Gennum()
# Bind SPEC object to FMC ADC card
#for name, value in spec.parse_addr(FMC_ADC_ADDR).iteritems():
# print "%9s:0x%04X"%(name, value)
#spec.bind(FMC_ADC_ADDR)
# Load FMC ADC firmware
print "Loading FMC ADC firmware: %s\n" % FMC_ADC_BITSTREAM
spec.load_firmware(FMC_ADC_BITSTREAM)
time.sleep(2)
# Carrier object declaration (SPEC board specific part)
try:
carrier = CFmcAdc100mSpec(spec, EXPECTED_BITSTREAM_TYPE)
except FmcAdc100mSpecOperationError as e:
raise PtsCritical("Carrier init failed, test stopped: %s" % e)
print("Try to read outside the mapped wishbone address range:")
for addr in range(0x0, 0x30, 0x4):
print("0x%02X: 0x%08X"%(addr, carrier.csr.rd_reg(addr)))
print "==> End of test%02d" % TEST_NB
print "================================================================================"
end_test_time = time.time()
print "Test%02d elapsed time: %.2f seconds\n" % (TEST_NB, end_test_time-start_test_time)
if __name__ == '__main__' :
main()
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