Commit ed3b3880 authored by Matthieu Cattin's avatar Matthieu Cattin

fmcadc100m_csr: Fix Sampling clock reg description.

parent 353cfc0d
......@@ -44,7 +44,7 @@ FMCADC100M_CSR=['FMC ADC 100MS/s core registers',{
'NB':[0, 'Number of remaining shots', 0xFFFF],
'RESERVED':[16, 'Reserved', 0xFFFF]}],
'TRIG_POS':[0x1C, 'Trigger address register', {}],
'FS_FREQ':[0x20, 'Sample rate', {}],
'FS_FREQ':[0x20, 'Sampling clock [Hz]', {}],
'SR':[0x24, 'Sample rate', {
'DECI':[0, 'Sample rate decimation factor', 0xFFFFFFFF]}],
'PRE_SAMPLES':[0x28, 'Pre-trigger samples', {}],
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