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FMC ADC 100M 14b 4cha - Testing
Commit a549b309 authored by Matthieu Cattin's avatar Matthieu Cattin
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fmc_adc_spec: Add verbose param, remove unsless 3sec sleep.

parent 3590e175
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Showing with 15 additions and 9 deletions
test/fmcadc100m14b4cha/python/fmc_adc_spec.py
View file @ a549b309
......@@ -470,13 +470,14 @@ class CFmcAdc100mSpec:
# Writes data pattern to carrier's DDR memory
def put_data(self, carrier_addr, pattern, length):
def put_data(self, carrier_addr, pattern, length, verbose=False):
# Configure DMA
items_required = int(math.ceil(length/float(self.DMA_LENGTH)))
if(128 < items_required):
print('Required items: %d')%items_required
raise Exception('Current gn4124 class only supports up to 128 items.')
print('Required items: %d')%items_required
if verbose:
print('Required items: %d')%items_required
for num in range(items_required):
if(items_required == num+1):
next_item = 0
......@@ -498,20 +499,24 @@ class CFmcAdc100mSpec:
# Write pattern to DMA reserved host memory pages
for page in range(1,items_required):
print("Writting %8X pattern on host memory page %d"%(pattern, page))
if verbose:
print("Writting %8X pattern on host memory page %d"%(pattern, page))
self.gnum.set_memory_page(page, pattern)
#self.print_irq_controller_regs()
time.sleep(3)
#time.sleep(3)
# Start DMA
self.gnum.start_dma()
# Wait for end of DMA interrupt
print('Wait GN4124 interrupt')
if verbose:
print('Wait GN4124 interrupt')
self.gnum.wait_irq()
print('GN4124 interrupt occured')
if verbose:
print('GN4124 interrupt occured')
dma_finished = 0
self.print_irq_controller_regs()
#print('irq mask:%.4X')%self.get_irq_en_mask()
if verbose:
self.print_irq_controller_regs()
print('irq mask:%.4X')%self.get_irq_en_mask()
while(0 == dma_finished):
irq_src = self.get_irq_source()
#print('IRQ source : %.4X')%irq_src
......@@ -522,6 +527,7 @@ class CFmcAdc100mSpec:
#print('IRQ source : %.4X')%self.get_irq_source()
dma_finished = 1
time.sleep(0.005)
print('DMA finished!')
if verbose:
print('DMA finished!')
###########################################################################
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