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FMC ADC 100M 14b 4cha - Testing
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FMC ADC 100M 14b 4cha - Testing
Commits
90d53cc3
Commit
90d53cc3
authored
Nov 21, 2012
by
Matthieu Cattin
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Modify wishbone modules base addresses for SDB enabled firmware.
parent
b2e5e2d0
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2 changed files
with
10 additions
and
10 deletions
+10
-10
fmc_adc.py
test/fmcadc100m14b4cha/python/fmc_adc.py
+5
-5
fmc_adc_spec.py
test/fmcadc100m14b4cha/python/fmc_adc_spec.py
+5
-5
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test/fmcadc100m14b4cha/python/fmc_adc.py
View file @
90d53cc3
...
...
@@ -75,19 +75,19 @@ class FmcAdc100mOperationError(Exception):
class
CFmcAdc100m
:
FMC_SYS_I2C_ADDR
=
0x
600
00
FMC_SYS_I2C_ADDR
=
0x
16
00
EEPROM_ADDR
=
0x50
FMC_SPI_ADDR
=
0x
700
00
FMC_SPI_ADDR
=
0x
17
00
FMC_SPI_DIV
=
100
FMC_SPI_SS
=
{
'ADC'
:
0
,
'DAC1'
:
1
,
'DAC2'
:
2
,
'DAC3'
:
3
,
'DAC4'
:
4
}
FMC_I2C_ADDR
=
0x
800
00
FMC_I2C_ADDR
=
0x
18
00
SI570_ADDR
=
0x55
FMC_ONEWIRE_ADDR
=
0x
A00
00
FMC_ONEWIRE_ADDR
=
0x
1A
00
FMC_CSR_ADDR
=
0x
900
00
FMC_CSR_ADDR
=
0x
19
00
"""
...
...
test/fmcadc100m14b4cha/python/fmc_adc_spec.py
View file @
90d53cc3
...
...
@@ -36,11 +36,11 @@ class FmcAdc100mSpecOperationError(Exception):
class
CFmcAdc100mSpec
:
# Wishbone core base addresses
GNUM_DMA_CSR_ADDR
=
0x
00
000
ONEWIRE_ADDR
=
0x
200
00
CSR_ADDR
=
0x
300
00
UTC_CORE_ADDR
=
0x
400
00
IRQ_CONTROLLER_ADDR
=
0x
500
00
GNUM_DMA_CSR_ADDR
=
0x
1
000
ONEWIRE_ADDR
=
0x
12
00
CSR_ADDR
=
0x
13
00
UTC_CORE_ADDR
=
0x
14
00
IRQ_CONTROLLER_ADDR
=
0x
15
00
# Onewire core port
DS18B20_PORT
=
0
...
...
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