Skip to content

F
FMC ADC 100M 14b 4cha - Testing
Commit 8c14b2b4 authored by Matthieu Cattin's avatar Matthieu Cattin
Browse files
Options

test28: Work on random acquisition setup.

parent a549b309
Hide whitespace changes
Inline Side-by-side
Showing with 135 additions and 24 deletions
test/fmcadc100m14b4cha/python/test28.py 100644 → 100755
View file @ 8c14b2b4
......@@ -9,6 +9,7 @@
import sys
import time
import os
import random as rdm
# Add common modules and libraries location to path
sys.path.append('../../../')
......@@ -20,6 +21,7 @@ from ptsexcept import *
import rr
# Import specific modules
from fmc_adc_spec import *
from fmc_adc import *
from numpy import *
......@@ -27,7 +29,7 @@ from pylab import *
from ctypes import *
from calibr_box import *
from cp210x_eeprom import *
import find_usb_tty
from find_usb_tty import *
from PAGE.Agilent33250A import *
from PAGE.SineWaveform import *
......@@ -35,21 +37,21 @@ from PAGE.SineWaveform import *
"""
test28: Long term test
1) Configure acquisition with random params
2) Configure waveform generator to generate a sine wave within the acquisition params
3) Perform acquisition
4) Fit acquired waveform to a sine wave and check that it's within boundaries
1) Clear DDR memory
2) Configure acquisition with random params
3) Configure waveform generator to generate a sine wave within the acquisition params
4) Perform acquisition
5) Fit acquired waveform to a sine wave and check that it's within boundaries
"""
##################################################
# Constants declaration
##################################################
################################################################################
# Constants declaration
################################################################################
TEST_NB = 28
# Gateware
FMC_ADC_BITSTREAM = '../firmwares/spec-fmc-adc-v1.0.bin'
FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM)
EXPECTED_BITSTREAM_TYPE = 0x0
# Calibration box
......@@ -67,20 +69,78 @@ AWG_SET_SLEEP = 0.3
NB_CHANNELS = 4
SSR_SET_SLEEP = 0.05
DAC_SET_SLEEP = 0.01 # in [s]
SAMPLE_WIDTH = 2 # bytes
MEMORY_SIZE = 2^28/(NB_CHANNELS * SAMPLE_WIDTH) # samples
MULTISHOT_MAX_SIZE = 2^11 # samples
ACQ_TIMEOUT = 10
SAMP_FREQ = 100E6 # Hz
MIN_PRE_TRIG_SAMPLES = 0
MAX_PRE_TRIG_SAMPLES = 2^25
MIN_POST_TRIG_SAMPLES = 0
MAX_POST_TRIG_SAMPLES = 2^25
MIN_NB_SHOTS = 1
MAX_NB_SHOTS =
# Acquisition
ACQ_MIN_PERIODS = 2
# Input waveform
SINE_MIN_FREQ = 10E3 # Hz
SINE_MAX_FREQ = 1E6 # Hz
SINE_MIN_AMPL = 0.05 # Vpeak
SINE_MAX_AMPL = 5.0 # Vpeak
ACQ_TIMEOUT = 10
################################################################################
# Functions declaration
################################################################################
def clear_ddr(carrier, verbose=False):
# dma item size = 4096 bytes
# max linked items = 128
# 2^25/(4096*128) = 64
item_size = 4096
max_items = 128
pattern = 0x0
carrier.set_irq_en_mask(0x1)
if verbose:
print("Clearing DDR memory")
for i in range(64):
carrier.put_data(i*item_size*max_items, pattern, item_size*max_items)
if verbose:
print("DMA #%d"%i)
def set_awg(awg, freq, ampl, offset, verbose=False):
# Set sine params
sine = SineWaveform()
sine.frequency = freq # Hz
sine.amplitude = ampl # Vpeak
sine.dc = offset # V
if verbose:
print('AWG Sine frequency:%3.3fMHz amplitude:%2.3fVp offset:%2.3fV')%(sine.frequency/1E6, sine.amplitude, sine.dc)
# Set AWG
awg.connect()
awg.play(sine)
awg.output = True
def get_best_input_range(in_ampl, term):
# If the 50 ohms termination is enabled, input amplitude is reduced by a factor 2
if term == 'ON':
in_ampl = in_ampl/2.0
in_range = '100mV'
if in_ampl > 0.05:
in_range = '1V'
if in_ampl > 0.5:
in_range = '10V'
return in_range
def set_acq():
# Set acquisition
fmc.set_pre_trig_samples(PRE_TRIG_SAMPLES)
fmc.set_post_trig_samples(POST_TRIG_SAMPLES)
fmc.set_shots(NB_SHOTS)
set_trig_config(hw_sel, hw_pol, hw_en, sw_en, channel, int_thres, delay)
set_decimation(factor)
set_input_term(channel, state)
set_dc_offset(channel, value)
set_input_range(channel, in_range)
......@@ -145,6 +205,20 @@ def acq_mean(acq_data):
mean_d.append(mean(acq_data[channel-1::4]))
return mean_d
def plot_all(data, ylimit):
sample = arange(len(data)/4)
clf()
plot(sample, data[0::4], 'b', label='Channel 1')
plot(sample, data[1::4], 'g', label='Channel 2')
plot(sample, data[2::4], 'c', label='Channel 3')
plot(sample, data[3::4], 'm', label='Channel 4')
ylim(-ylimit-(ylimit/10.0), ylimit+(ylimit/10.0))
xlim(0, len(sample))
grid(which='both')
legend()
draw()
show()
return 0
def main (default_directory='.'):
......@@ -159,9 +233,10 @@ def main (default_directory='.'):
spec = rr.Gennum()
# Load FMC ADC firmware
print "Loading FMC ADC firmware: %s\n" % FMC_ADC_BITSTREAM
spec.load_firmware(FMC_ADC_BITSTREAM)
time.sleep(2)
bitstream_path = os.path.join(default_directory, FMC_ADC_BITSTREAM)
#print "Loading FMC ADC firmware: %s\n" % bitstream_path
#spec.load_firmware(bitstream_path)
#time.sleep(2)
# Carrier object declaration (SPEC board specific part)
# Used to check that the firmware is loaded.
......@@ -180,16 +255,52 @@ def main (default_directory='.'):
try:
# Others objects declaration
usb_tty = find_usb_tty.CttyUSB()
usb_tty = CttyUSB()
awg_tty = usb_tty.find_usb_tty(AWG_USB_VENDOR_ID, AWG_USB_PRODUCT_ID)
box_tty = usb_tty.find_usb_tty(BOX_USB_VENDOR_ID, BOX_USB_PRODUCT_ID)
gen = Agilent33250A(device=awg_tty[0], bauds=AWG_BAUD)
sine = SineWaveform()
box = calibr_box.CCalibr_box(box_tty[0])
awg = Agilent33250A(device=awg_tty[0], bauds=AWG_BAUD)
box = CCalibr_box(box_tty[0])
print("Clearing DDR memory...")
t1 = time.time()
#clear_ddr(carrier, False)
t2 = time.time()
print "elapsed time: %.2f seconds\n" % (t2-t1)
print("Building input sine wave...")
sine_freq = SINE_MIN_FREQ + ((SINE_MAX_FREQ-SINE_MIN_FREQ)*rdm.random())
sine_ampl = SINE_MIN_AMPL + ((SINE_MAX_AMPL-SINE_MIN_AMPL)*rdm.random())
sine_off = (SINE_MAX_AMPL-sine_ampl)*rdm.random()
print("Input sine wave => Frequency: %3.3fMHz, Amplitude: %2.3fVp, Offset: %2.3fV"%(sine_freq/1E6, sine_ampl, sine_off))
print("Setting AWG...")
set_awg(awg, sine_freq, sine_ampl, sine_off)
print("Choosing input termination...")
adc_term = rdm.choice(['ON', 'OFF'])
print("Input termination: %s"%adc_term)
print("Finding best adc input range...")
adc_range = get_best_input_range(sine_ampl, adc_term)
print("Selected input range: %s"%adc_range)
# min_periods = 2
# samp_freq = 100E6
# sine_freq = x
# => min_samples = 2*samp_freq/sine_freq
acq_min_samples = ACQ_MIN_PERIODS*SAMP_FREQ/sine_freq
print("Minimum number of samples: %d"%acq_min_samples)
#acq_samples = acq_min_samples +
# acq_max_nb_shots =
#data = carrier.get_data(0, 50000*8)
#plot_all(data, max(data))
sys.exit()
# Configuration
acq_config(fmc)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment