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FMC ADC 100M 14b 4cha - Testing
Commit 67075ccc authored by Matthieu Cattin's avatar Matthieu Cattin
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test17: Fix data retreive range, change bitstream to load (release v1.0).

parent d570e70e
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Showing with 4 additions and 16 deletions
test/fmcadc100m14b4cha/python/test17.py
View file @ 67075ccc
......@@ -59,7 +59,7 @@ ACQ_TIMEOUT = 10
MAX_FIRMWARE_RELOAD = 10
PRE_TRIG_SAMPLES = 1000
PRE_TRIG_SAMPLES = 2000
POST_TRIG_SAMPLES = 50000
NB_SHOTS = 1
......@@ -71,19 +71,6 @@ DAC_NBITS = 16
DAC_FS = 10 # DAC full scale range is 10V
def load_firmware(default_directory):
print('Load firmware to FPGA')
path_fpga_loader = '../../../gnurabbit/user/fpga_loader';
path_firmware = '../firmwares/spec_fmcadc100m14b4cha.bin';
firmware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_firmware)
print firmware_loader + ' ' + bitstream
os.system( firmware_loader + ' ' + bitstream )
time.sleep(2);
def disconnect_channels(fmc):
for i in range(1,NB_CHANNELS+1):
fmc.set_ssr(i, 0x00)
......@@ -137,7 +124,7 @@ def acquisition_all(fmc, spec_fmc):
# Retrieve data trough DMA
trig_pos = fmc.get_trig_pos()
print('Trigger position; 0x%X')%(trig_pos)
channels_data = spec_fmc.get_data((trig_pos<<3), ACQ_LENGTH*8)
channels_data = spec_fmc.get_data(((trig_pos-PRE_TRIG_SAMPLES)<<3), (PRE_TRIG_SAMPLES+POST_TRIG_SAMPLES)*8)
return channels_data
......@@ -154,6 +141,7 @@ def plot_all(data, mean, ylimit):
plot(sample, [mean[2]]*len(sample), 'r')
plot(sample, [mean[3]]*len(sample), 'r')
ylim(-ylimit-(ylimit/10.0), ylimit+(ylimit/10.0))
xlim(0, len(sample))
grid(which='both')
legend()
draw()
......@@ -204,7 +192,7 @@ def main (default_directory = '.'):
# Constants declaration
TEST_NB = 19
EXPECTED_BITSTREAM_TYPE = 0x1
FMC_ADC_BITSTREAM = '../firmwares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM = '../firmwares/spec-fmc-adc-v1.0.bin'
FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM)
# Objects declaration
......
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