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FMC ADC 100M 14b 4cha - Testing
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FMC ADC 100M 14b 4cha - Testing
Commits
63746a35
Commit
63746a35
authored
Jan 30, 2014
by
Matthieu Cattin
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fmc_adc: Use byte addresses for DDR read function.
parent
1b425081
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1 changed file
with
6 additions
and
4 deletions
+6
-4
fmc_adc.py
test/fmcadc100m14b4cha/python/fmc_adc.py
+6
-4
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test/fmcadc100m14b4cha/python/fmc_adc.py
View file @
63746a35
...
...
@@ -213,6 +213,7 @@ class CFmcAdc100m:
# Dump SDB records
def
sdb_dump
(
self
):
print
(
"SDB address: 0x
%
x"
%
(
self
.
adc_mezz_offset
+
self
.
SDB_ADDR
))
self
.
sdb
.
dump
()
...
...
@@ -927,19 +928,20 @@ class CFmcAdc100m:
# DDR memory interface, FOR SVEC ONLY
# Read data from DDR
# carrier_addr and length are in
32-bit word
# carrier_addr and length are in
bytes
def
get_data
(
self
,
carrier_addr
,
length
,
raw
=
False
):
ret
=
[]
data
=
[]
cc
=
self
.
bus
.
iwrite
(
0
,
self
.
DDR_ADR_ADDR
,
4
,
carrier_addr
)
cc
=
self
.
bus
.
iwrite
(
0
,
self
.
DDR_ADR_ADDR
,
4
,
carrier_addr
/
4
)
#print('[get_data] write: addr=0x%.8X cc=%d'%(self.DDR_ADR_ADDR, cc))
for
i
in
range
(
length
):
# length param is byte, but we're reading 32-bit words -> length/4
for
i
in
range
(
length
/
4
):
#adr_cnt_b = self.bus.iread(0, self.DDR_ADR_ADDR, 4)
data
.
append
(
self
.
bus
.
iread
(
0
,
self
.
DDR_DAT_ADDR
,
4
))
#print('[get_data] read: addr=0x%.9X i=%d'%(self.DDR_DAT_ADDR, i))
#adr_cnt = self.bus.iread(0, self.DDR_ADR_ADDR, 4)
#print('[get_data] address counter: before=0x%.8X after=0x%.8X'%(adr_cnt_b, adr_cnt))
for
i
in
range
(
length
):
for
i
in
range
(
length
/
4
):
ret
.
append
(
data
[
i
]
&
0xFFFF
)
ret
.
append
(
data
[
i
]
>>
16
)
if
raw
:
...
...
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