Commit 239434ba authored by Matthieu Cattin's avatar Matthieu Cattin

struct: Update VME tests paths to fit new folder structure.

parent adc00413
pts @ f9d07331
Subproject commit 09ed4c4bb283b0dacd6ed36d016b85a26169b371 Subproject commit f9d07331c1477487a9fae97284beb1fb4c14c4d3
...@@ -9,10 +9,17 @@ ...@@ -9,10 +9,17 @@
# Import standard modules # Import standard modules
import sys import sys
import os
import time import time
import random import random
import math import math
# Add common modules and libraries location to path
cdir = os.path.dirname(os.path.realpath(__file__))
sys.path.append(os.path.join(cdir,'../pts/'))
sys.path.append(os.path.join(cdir,'../pts/common/'))
sys.path.append(os.path.join(cdir,'../../svec_pts/ubuntu/pts/pyts/'))
# Import specific modules # Import specific modules
from sdb import * from sdb import *
from csr import * from csr import *
......
#! ./python #! /usr/bin/env python
# coding: utf8 # coding: utf8
# Copyright CERN, 2013 # Copyright CERN, 2013
...@@ -11,21 +11,16 @@ import sys ...@@ -11,21 +11,16 @@ import sys
import time import time
import os import os
# Add common modules and libraries location to path # Import specific modules
sys.path.append('../../../') from fmc_adc_svec import *
sys.path.append('../../../common/')
sys.path.append('../../../../svec_pts/ubuntu/pts/pyts/')
# Import common modules # Import common modules
from ptsexcept import * from ptsexcept import *
from rr2vv import * from rr2vv import *
# Import specific modules
from fmc_adc_svec import *
""" """
test00: Load firmware, verify firmware type and test mezzanine presence line. test00: Load gateware, verify gateware type and test mezzanine presence line.
""" """
def main (default_directory='.'): def main (default_directory='.'):
...@@ -33,7 +28,7 @@ def main (default_directory='.'): ...@@ -33,7 +28,7 @@ def main (default_directory='.'):
# Constants declaration # Constants declaration
LUN = 0 LUN = 0
TEST_NB = 0 TEST_NB = 0
FMC_ADC_BITSTREAM = '../../../../../firmwares/svec_fmcadc100m14b4cha.bin' FMC_ADC_BITSTREAM = '../../gatewares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM) FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM)
EXPECTED_BITSTREAM_TYPE = 0x0 EXPECTED_BITSTREAM_TYPE = 0x0
...@@ -48,8 +43,8 @@ def main (default_directory='.'): ...@@ -48,8 +43,8 @@ def main (default_directory='.'):
print "Initialising device.\n" print "Initialising device.\n"
bus.vv_init() bus.vv_init()
# Load FMC ADC firmware # Load FMC ADC gateware
print "Loading FMC ADC firmware: %s\n" % FMC_ADC_BITSTREAM print "Loading FMC ADC gateware: %s\n" % FMC_ADC_BITSTREAM
ret = bus.vv_load(FMC_ADC_BITSTREAM, 1) ret = bus.vv_load(FMC_ADC_BITSTREAM, 1)
print('') print('')
time.sleep(2) time.sleep(2)
......
...@@ -11,19 +11,14 @@ import sys ...@@ -11,19 +11,14 @@ import sys
import time import time
import os import os
# Add common modules and libraries location to path # Import specific modules
sys.path.append('../../../') from fmc_adc_svec import *
sys.path.append('../../../common/') from fmc_adc import *
sys.path.append('../../../../svec_pts/ubuntu/pts/pyts/')
# Import common modules # Import common modules
from ptsexcept import * from ptsexcept import *
from rr2vv import * from rr2vv import *
# Import specific modules
from fmc_adc_svec import *
from fmc_adc import *
""" """
svec_test01: Test mezzanines (all peripherals, 1-wire, i2c, spi, etc...) svec_test01: Test mezzanines (all peripherals, 1-wire, i2c, spi, etc...)
...@@ -35,7 +30,7 @@ def main (default_directory='.'): ...@@ -35,7 +30,7 @@ def main (default_directory='.'):
# Constants declaration # Constants declaration
LUN = 0 LUN = 0
TEST_NB = 1 TEST_NB = 1
FMC_ADC_BITSTREAM = '../../../../../firmwares/svec_fmcadc100m14b4cha.bin' FMC_ADC_BITSTREAM = '../../gatewares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM) FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM)
EXPECTED_BITSTREAM_TYPE = 0x0 EXPECTED_BITSTREAM_TYPE = 0x0
NB_CHANNELS = 4 NB_CHANNELS = 4
...@@ -53,15 +48,15 @@ def main (default_directory='.'): ...@@ -53,15 +48,15 @@ def main (default_directory='.'):
bus = VME_rr_compatible(LUN) bus = VME_rr_compatible(LUN)
print "Initialising device.\n" print "Initialising device.\n"
# Load FMC ADC firmware # Load FMC ADC gateware
ask = 'N' ask = 'N'
while ((ask != "Y") and (ask != "N")) : while ((ask != "Y") and (ask != "N")) :
ask = raw_input("Do you want to load the firmware: %s? [y,n]"%(FMC_ADC_BITSTREAM)) ask = raw_input("Do you want to load the gateware: %s? [y,n]"%(FMC_ADC_BITSTREAM))
ask = ask.upper() ask = ask.upper()
print " " print " "
if (ask == "Y"): if (ask == "Y"):
print "Loading FMC ADC firmware: %s\n" % FMC_ADC_BITSTREAM print "Loading FMC ADC gateware: %s\n" % FMC_ADC_BITSTREAM
bus.vv_init() bus.vv_init()
ret = bus.vv_load(FMC_ADC_BITSTREAM, 1) ret = bus.vv_load(FMC_ADC_BITSTREAM, 1)
print('') print('')
...@@ -188,20 +183,25 @@ def main (default_directory='.'): ...@@ -188,20 +183,25 @@ def main (default_directory='.'):
print('The external trigger input is working fine.') print('The external trigger input is working fine.')
# DDR access # DDR access
rd_size = 8 # 32-bit words
wr_size = rd_size/2
print('\nTest DDR access') print('\nTest DDR access')
ddr_data_rd = fmc[i].get_data(0x0, 16, raw=True) ddr_data_rd = fmc[i].get_data(0x0, rd_size*4, raw=True)
ddr_data_wr = range(8) ddr_data_wr = range(wr_size)
fmc[i].put_data(0x0, ddr_data_wr) fmc[i].put_data(0x0, ddr_data_wr)
ddr_data_wr.extend([0x0]*8) ddr_data_wr.extend([0x0]*wr_size)
ddr_data_rdb = fmc[i].get_data(0x0, 16, raw=True) ddr_data_rdb = fmc[i].get_data(0x0, rd_size*4, raw=True)
ddr_data_exp = ddr_data_wr[0:8] + ddr_data_rd[8:16] ddr_data_exp = ddr_data_wr[0:wr_size] + ddr_data_rd[wr_size:rd_size]
print('addr: read: written: read back expected:') print('addr: read: written: read back expected:')
for j in range(len(ddr_data_rd)): for j in range(len(ddr_data_rd)):
print('%.3d 0x%.8x 0x%.8x 0x%.8x 0x%.8x'%(j, ddr_data_rd[j], ddr_data_wr[j], ddr_data_rdb[j], ddr_data_exp[j])) print('%.3d 0x%.8x 0x%.8x 0x%.8x 0x%.8x'%(j, ddr_data_rd[j], ddr_data_wr[j], ddr_data_rdb[j], ddr_data_exp[j]))
print ddr_data_rdb
print ddr_data_exp
if ddr_data_rdb != ddr_data_exp: if ddr_data_rdb != ddr_data_exp:
error[i] = 'Error in ddr access' error[i] = 'Error in ddr access'
continue continue
......
...@@ -12,26 +12,21 @@ import sys ...@@ -12,26 +12,21 @@ import sys
import time import time
import os import os
# Add common modules and libraries location to path
sys.path.append('../../../')
sys.path.append('../../../common/')
sys.path.append('../../../../svec_pts/ubuntu/pts/pyts/')
# Import common modules
from ptsexcept import *
from rr2vv import *
# Import specific modules # Import specific modules
from fmc_adc_svec import * from fmc_adc_svec import *
from fmc_adc import * from fmc_adc import *
from numpy import * from numpy import *
# Import common modules
from ptsexcept import *
from rr2vv import *
""" """
svec_test12: Takes an aqcuisition of all channels and print it to a file svec_test12: Takes an aqcuisition of all channels and print it to a file
Set UTC and read UTC time-tags Set UTC and read UTC time-tags
Note: Requires svec_test00.py to run first to load the firmware! Note: Requires svec_test00.py to run first to load the gateware!
""" """
...@@ -55,7 +50,7 @@ def main (default_directory='.'): ...@@ -55,7 +50,7 @@ def main (default_directory='.'):
# Constants declaration # Constants declaration
LUN = 0 LUN = 0
TEST_NB = 12 TEST_NB = 12
FMC_ADC_BITSTREAM = '../../../../../firmwares/svec_fmcadc100m14b4cha.bin' FMC_ADC_BITSTREAM = '../../gatewares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM) FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM)
EXPECTED_BITSTREAM_TYPE = 0x0 EXPECTED_BITSTREAM_TYPE = 0x0
...@@ -69,7 +64,7 @@ def main (default_directory='.'): ...@@ -69,7 +64,7 @@ def main (default_directory='.'):
bus.vv_open() bus.vv_open()
# Carrier object declaration (SVEC board specific part) # Carrier object declaration (SVEC board specific part)
# Used to check that the firmware is loaded. # Used to check that the gateware is loaded.
try: try:
carrier = CFmcAdc100mSvec(bus, EXPECTED_BITSTREAM_TYPE) carrier = CFmcAdc100mSvec(bus, EXPECTED_BITSTREAM_TYPE)
except FmcAdc100mSvecOperationError as e: except FmcAdc100mSvecOperationError as e:
......
...@@ -12,25 +12,20 @@ import sys ...@@ -12,25 +12,20 @@ import sys
import time import time
import os import os
# Add common modules and libraries location to path
sys.path.append('../../../')
sys.path.append('../../../common/')
sys.path.append('../../../../svec_pts/ubuntu/pts/pyts/')
# Import common modules
from ptsexcept import *
from rr2vv import *
# Import specific modules # Import specific modules
from fmc_adc_svec import * from fmc_adc_svec import *
from fmc_adc import * from fmc_adc import *
from numpy import * from numpy import *
# Import common modules
from ptsexcept import *
from rr2vv import *
""" """
svec_test30: Test software reset. svec_test30: Test software reset.
Note: Requires test00.py to run first to load the firmware! Note: Requires test00.py to run first to load the gateware!
""" """
...@@ -109,7 +104,7 @@ def main (default_directory='.'): ...@@ -109,7 +104,7 @@ def main (default_directory='.'):
# Constants declaration # Constants declaration
LUN = 0 LUN = 0
TEST_NB = 30 TEST_NB = 30
FMC_ADC_BITSTREAM = '../../../../../firmwares/svec_fmcadc100m14b4cha.bin' FMC_ADC_BITSTREAM = '../../gatewares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM) FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM)
EXPECTED_BITSTREAM_TYPE = 0x0 EXPECTED_BITSTREAM_TYPE = 0x0
...@@ -128,14 +123,14 @@ def main (default_directory='.'): ...@@ -128,14 +123,14 @@ def main (default_directory='.'):
print "Initialising device.\n" print "Initialising device.\n"
bus.vv_init() bus.vv_init()
# Load FMC ADC firmware # Load FMC ADC gateware
print "Loading FMC ADC firmware: %s\n" % FMC_ADC_BITSTREAM print "Loading FMC ADC gateware: %s\n" % FMC_ADC_BITSTREAM
ret = bus.vv_load(FMC_ADC_BITSTREAM, 1) ret = bus.vv_load(FMC_ADC_BITSTREAM, 1)
print('') print('')
time.sleep(2) time.sleep(2)
# Carrier object declaration (SPEC board specific part) # Carrier object declaration (SPEC board specific part)
# Used to check that the firmware is loaded. # Used to check that the gateware is loaded.
try: try:
carrier = CFmcAdc100mSvec(bus, EXPECTED_BITSTREAM_TYPE) carrier = CFmcAdc100mSvec(bus, EXPECTED_BITSTREAM_TYPE)
except FmcAdc100mSvecOperationError as e: except FmcAdc100mSvecOperationError as e:
......
...@@ -11,19 +11,14 @@ import sys ...@@ -11,19 +11,14 @@ import sys
import time import time
import os import os
# Add common modules and libraries location to path # Import specific modules
sys.path.append('../../../') from fmc_adc_svec import *
sys.path.append('../../../common/') from fmc_adc import *
sys.path.append('../../../../svec_pts/ubuntu/pts/pyts/')
# Import common modules # Import common modules
from ptsexcept import * from ptsexcept import *
from rr2vv import * from rr2vv import *
# Import specific modules
from fmc_adc_svec import *
from fmc_adc import *
""" """
test34: Test interrupts test34: Test interrupts
...@@ -36,7 +31,7 @@ def main (default_directory='.'): ...@@ -36,7 +31,7 @@ def main (default_directory='.'):
# Constants declaration # Constants declaration
LUN = 0 LUN = 0
TEST_NB = 34 TEST_NB = 34
FMC_ADC_BITSTREAM = '../../../../../firmwares/svec_fmcadc100m14b4cha.bin' FMC_ADC_BITSTREAM = '../../gatewares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM) FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM)
EXPECTED_BITSTREAM_TYPE = 0x0 EXPECTED_BITSTREAM_TYPE = 0x0
NB_CHANNELS = 4 NB_CHANNELS = 4
...@@ -55,15 +50,15 @@ def main (default_directory='.'): ...@@ -55,15 +50,15 @@ def main (default_directory='.'):
bus = VME_rr_compatible(LUN) bus = VME_rr_compatible(LUN)
print "Initialising device.\n" print "Initialising device.\n"
# Load FMC ADC firmware # Load FMC ADC gateware
ask = '' ask = ''
while ((ask != "Y") and (ask != "N")) : while ((ask != "Y") and (ask != "N")) :
ask = raw_input("Do you want to load the firmware: %s? [y,n]"%(FMC_ADC_BITSTREAM)) ask = raw_input("Do you want to load the gateware: %s? [y,n]"%(FMC_ADC_BITSTREAM))
ask = ask.upper() ask = ask.upper()
print " " print " "
if (ask == "Y"): if (ask == "Y"):
print "Loading FMC ADC firmware: %s\n" % FMC_ADC_BITSTREAM print "Loading FMC ADC gateware: %s\n" % FMC_ADC_BITSTREAM
bus.vv_init() bus.vv_init()
ret = bus.vv_load(FMC_ADC_BITSTREAM, 1) ret = bus.vv_load(FMC_ADC_BITSTREAM, 1)
print('') print('')
......
...@@ -12,25 +12,20 @@ import sys ...@@ -12,25 +12,20 @@ import sys
import time import time
import os import os
# Add common modules and libraries location to path
sys.path.append('../../../')
sys.path.append('../../../common/')
sys.path.append('../../../../svec_pts/ubuntu/pts/pyts/')
# Import common modules
from ptsexcept import *
from rr2vv import *
# Import specific modules # Import specific modules
from fmc_adc_svec import * from fmc_adc_svec import *
from fmc_adc import * from fmc_adc import *
from numpy import * from numpy import *
# Import common modules
from ptsexcept import *
from rr2vv import *
""" """
svec_test36: Test SDB records. svec_test36: Test SDB records.
Note: Requires test00.py to run first to load the firmware! Note: Requires test00.py to run first to load the gateware!
""" """
...@@ -39,7 +34,7 @@ def main (default_directory='.'): ...@@ -39,7 +34,7 @@ def main (default_directory='.'):
# Constants declaration # Constants declaration
LUN = 0 LUN = 0
TEST_NB = 36 TEST_NB = 36
FMC_ADC_BITSTREAM = '../../../../../firmwares/svec_fmcadc100m14b4cha.bin' FMC_ADC_BITSTREAM = '../../gatewares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM) FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM)
EXPECTED_BITSTREAM_TYPE = 0x0 EXPECTED_BITSTREAM_TYPE = 0x0
...@@ -58,14 +53,14 @@ def main (default_directory='.'): ...@@ -58,14 +53,14 @@ def main (default_directory='.'):
print "Initialising device.\n" print "Initialising device.\n"
bus.vv_init() bus.vv_init()
# Load FMC ADC firmware # Load FMC ADC gateware
print "Loading FMC ADC firmware: %s\n" % FMC_ADC_BITSTREAM print "Loading FMC ADC gateware: %s\n" % FMC_ADC_BITSTREAM
ret = bus.vv_load(FMC_ADC_BITSTREAM, 1) ret = bus.vv_load(FMC_ADC_BITSTREAM, 1)
print('') print('')
time.sleep(2) time.sleep(2)
# Carrier object declaration (SPEC board specific part) # Carrier object declaration (SPEC board specific part)
# Used to check that the firmware is loaded. # Used to check that the gateware is loaded.
try: try:
carrier = CFmcAdc100mSvec(bus, EXPECTED_BITSTREAM_TYPE) carrier = CFmcAdc100mSvec(bus, EXPECTED_BITSTREAM_TYPE)
except FmcAdc100mSvecOperationError as e: except FmcAdc100mSvecOperationError as e:
......
...@@ -12,24 +12,20 @@ import sys ...@@ -12,24 +12,20 @@ import sys
import time import time
import os import os
# Add common modules and libraries location to path # Import specific modules
sys.path.append('../../../') from fmc_adc_svec import *
sys.path.append('../../../common/') from fmc_adc import *
sys.path.append('../../../../svec_pts/ubuntu/pts/pyts/') from numpy import *
# Import common modules # Import common modules
from ptsexcept import * from ptsexcept import *
from rr2vv import * from rr2vv import *
# Import specific modules
from fmc_adc_svec import *
from fmc_adc import *
from numpy import *
""" """
svec_test37: Test trigger timetags (single and multi shot modes) svec_test37: Test trigger timetags (single and multi shot modes)
Note: Requires test00.py to run first to load the firmware! Note: Requires test00.py to run first to load the gateware!
""" """
NB_CHANNELS = 4 NB_CHANNELS = 4
...@@ -106,7 +102,7 @@ def main (default_directory='.'): ...@@ -106,7 +102,7 @@ def main (default_directory='.'):
# Constants declaration # Constants declaration
LUN = 0 LUN = 0
TEST_NB = 37 TEST_NB = 37
FMC_ADC_BITSTREAM = '../../../../../firmwares/svec_fmcadc100m14b4cha.bin' FMC_ADC_BITSTREAM = '../../gatewares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM) FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM)
EXPECTED_BITSTREAM_TYPE = 0x0 EXPECTED_BITSTREAM_TYPE = 0x0
...@@ -122,14 +118,14 @@ def main (default_directory='.'): ...@@ -122,14 +118,14 @@ def main (default_directory='.'):
print "Initialising device.\n" print "Initialising device.\n"
bus.vv_init() bus.vv_init()
# Load FMC ADC firmware # Load FMC ADC gateware
print "Loading FMC ADC firmware: %s\n" % FMC_ADC_BITSTREAM print "Loading FMC ADC gateware: %s\n" % FMC_ADC_BITSTREAM
ret = bus.vv_load(FMC_ADC_BITSTREAM, 1) ret = bus.vv_load(FMC_ADC_BITSTREAM, 1)
print('') print('')
time.sleep(2) time.sleep(2)
# Carrier object declaration (SVEC board specific part) # Carrier object declaration (SVEC board specific part)
# Used to check that the firmware is loaded. # Used to check that the gateware is loaded.
try: try:
carrier = CFmcAdc100mSvec(bus, EXPECTED_BITSTREAM_TYPE) carrier = CFmcAdc100mSvec(bus, EXPECTED_BITSTREAM_TYPE)
except FmcAdc100mSvecOperationError as e: except FmcAdc100mSvecOperationError as e:
......
...@@ -11,20 +11,15 @@ import sys ...@@ -11,20 +11,15 @@ import sys
import time import time
import os import os
# Add common modules and libraries location to path
sys.path.append('../../../')
sys.path.append('../../../common/')
sys.path.append('../../../../svec_pts/ubuntu/pts/pyts/')
# Import common modules
from ptsexcept import *
from rr2vv import *
# Import specific modules # Import specific modules
from fmc_adc_svec import * from fmc_adc_svec import *
from fmc_adc import * from fmc_adc import *
from numpy import * from numpy import *
# Import common modules
from ptsexcept import *
from rr2vv import *
""" """
svec_test42: Tests sampling frequency counter svec_test42: Tests sampling frequency counter
...@@ -35,7 +30,7 @@ def main (default_directory='.'): ...@@ -35,7 +30,7 @@ def main (default_directory='.'):
# Constants declaration # Constants declaration
LUN = 0 LUN = 0
TEST_NB = 42 TEST_NB = 42
FMC_ADC_BITSTREAM = '../../../../../firmwares/svec_fmcadc100m14b4cha.bin' FMC_ADC_BITSTREAM = '../../gatewares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM) FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM)
EXPECTED_BITSTREAM_TYPE = 0x0 EXPECTED_BITSTREAM_TYPE = 0x0
NB_CHANNELS = 4 NB_CHANNELS = 4
...@@ -53,15 +48,15 @@ def main (default_directory='.'): ...@@ -53,15 +48,15 @@ def main (default_directory='.'):
bus = VME_rr_compatible(LUN) bus = VME_rr_compatible(LUN)
print "Initialising device.\n" print "Initialising device.\n"
# Load FMC ADC firmware # Load FMC ADC gateware
ask = '' ask = ''
while ((ask != "Y") and (ask != "N")) : while ((ask != "Y") and (ask != "N")) :
ask = raw_input("Do you want to load the firmware: %s? [y,n]"%(FMC_ADC_BITSTREAM)) ask = raw_input("Do you want to load the gateware: %s? [y,n]"%(FMC_ADC_BITSTREAM))
ask = ask.upper() ask = ask.upper()
print " " print " "
if (ask == "Y"): if (ask == "Y"):
print "Loading FMC ADC firmware: %s\n" % FMC_ADC_BITSTREAM print "Loading FMC ADC gateware: %s\n" % FMC_ADC_BITSTREAM
bus.vv_init() bus.vv_init()
ret = bus.vv_load(FMC_ADC_BITSTREAM, 1) ret = bus.vv_load(FMC_ADC_BITSTREAM, 1)
print('') print('')
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment