fmc_adc: Update memory map. Add fct to get 'config ok' flag.

-> fmc_eic and timetag core moved to mezzanine (behind bridge). -> ddr addr and data (for svec) moved.

fmc_adc: Update memory map. Add fct to get 'config ok' flag.
-> fmc_eic and timetag core moved to mezzanine (behind bridge). -> ddr addr and data (for svec) moved.
1b425081 · Matthieu Cattin · ea45b623 · 1b425081
Commit 1b425081 authored Jan 09, 2014 by Matthieu Cattin
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fmc_adc.py test/fmcadc100m14b4cha/python/fmc_adc.py +22 -22

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--- a/test/fmcadc100m14b4cha/python/fmc_adc.py
+++ b/test/fmcadc100m14b4cha/python/fmc_adc.py
@@ -61,12 +61,10 @@ class CFmcAdc100m:
    #------------------------------------
    # offsets from mezzanine base address
-    FMC_EIC_ADDR = 0x0
-    UTC_CORE_ADDR = 0x100
    # FOR SVEC ONLY
-    DDR_DAT_ADDR = 0x1000
+    DDR_ADR_ADDR = 0x2000
-    DDR_ADR_ADDR = 0x200
+    DDR_DAT_ADDR = 0x3000
    #------------------------------------
    # offsets from mezzanine + adc core base address
@@ -83,8 +81,10 @@ class CFmcAdc100m:
    SI570_ADDR = 0x55
    FMC_CSR_ADDR = 0x1300
    FMC_ONEWIRE_ADDR = 0x1400
+    FMC_EIC_ADDR = 0x1500
+    UTC_CORE_ADDR = 0x1600
    # ADC core CSR
    FSM_CMD_START = 0x1
@@ -109,7 +109,6 @@ class CFmcAdc100m:
    def __init__(self, bus, offset=0x2000):
        self.bus = bus
        self.adc_mezz_offset = offset
-        self.adc_core_offset = offset + 0x2000
        # FOR SVEC ONLY
        self.DDR_DAT_ADDR = self.adc_mezz_offset + self.DDR_DAT_ADDR
@@ -117,26 +116,26 @@ class CFmcAdc100m:
        try:
            # Mezzanine objects declaration
-            self.fmc_eic = CCSR(self.bus, self.adc_mezz_offset + self.FMC_EIC_ADDR, FMC_ADC_EIC_REGS)
-            self.utc_core = CCSR(self.bus, self.adc_mezz_offset + self.UTC_CORE_ADDR, UTC_CORE_REGS)
            # ADC core objects declaration
-            self.sdb_csr = CCSR(self.bus, self.adc_core_offset + self.SDB_ADDR)
+            self.sdb_csr = CCSR(self.bus, self.adc_mezz_offset + self.SDB_ADDR)
            self.sdb = CSDB(self.sdb_csr)
-            self.fmc_sys_i2c = COpenCoresI2C(self.bus, self.adc_core_offset + self.FMC_SYS_I2C_ADDR, 249)
+            self.fmc_sys_i2c = COpenCoresI2C(self.bus, self.adc_mezz_offset + self.FMC_SYS_I2C_ADDR, 249)
-            self.fmc_i2c = COpenCoresI2C(self.bus, self.adc_core_offset + self.FMC_I2C_ADDR, 249)
+            self.fmc_i2c = COpenCoresI2C(self.bus, self.adc_mezz_offset + self.FMC_I2C_ADDR, 249)
-            self.eeprom_24aa64 = C24AA64(self.fmc_sys_i2c, self.adc_core_offset + self.EEPROM_ADDR)
+            self.eeprom_24aa64 = C24AA64(self.fmc_sys_i2c, self.adc_mezz_offset + self.EEPROM_ADDR)
-            self.si570 = CSi57x(self.fmc_i2c, self.adc_core_offset + self.SI570_ADDR)
+            self.si570 = CSi57x(self.fmc_i2c, self.adc_mezz_offset + self.SI570_ADDR)
-            self.fmc_onewire = COpenCoresOneWire(self.bus, self.adc_core_offset + self.FMC_ONEWIRE_ADDR, 624, 124)
+            self.fmc_onewire = COpenCoresOneWire(self.bus, self.adc_mezz_offset + self.FMC_ONEWIRE_ADDR, 624, 124)
            self.ds18b20 = CDS18B20(self.fmc_onewire, 0)
-            self.fmc_spi = COpenCoresSPI(self.bus, self.adc_core_offset + self.FMC_SPI_ADDR, self.FMC_SPI_DIV)
+            self.fmc_spi = COpenCoresSPI(self.bus, self.adc_mezz_offset + self.FMC_SPI_ADDR, self.FMC_SPI_DIV)
            self.adc_cfg = CLTC217x(self.fmc_spi, self.FMC_SPI_SS['ADC'])
            self.dac_ch = []
            self.dac_ch.append(CMAX5442(self.fmc_spi, self.FMC_SPI_SS['DAC1']))
            self.dac_ch.append(CMAX5442(self.fmc_spi, self.FMC_SPI_SS['DAC2']))
            self.dac_ch.append(CMAX5442(self.fmc_spi, self.FMC_SPI_SS['DAC3']))
            self.dac_ch.append(CMAX5442(self.fmc_spi, self.FMC_SPI_SS['DAC4']))
-            self.fmc_adc_csr = CCSR(self.bus, self.adc_core_offset + self.FMC_CSR_ADDR, FMCADC100M_CSR)
+            self.fmc_adc_csr = CCSR(self.bus, self.adc_mezz_offset + self.FMC_CSR_ADDR, FMCADC100M_CSR)
+            self.fmc_eic = CCSR(self.bus, self.adc_mezz_offset + self.FMC_EIC_ADDR, FMC_ADC_EIC_REGS)
+            self.utc_core = CCSR(self.bus, self.adc_mezz_offset + self.UTC_CORE_ADDR, UTC_CORE_REGS)
            # Set channels gain to 1
@@ -344,10 +343,6 @@ class CFmcAdc100m:
        except CSRDeviceOperationError as e:
            raise FmcAdc100mSvecOperationError(e)
-    ###########################################################################
-    ##########                  Code to review                       ##########
    # Returns last trigger event time-tag
    def get_utc_trig_tag(self):
        tag = []
@@ -384,8 +379,6 @@ class CFmcAdc100m:
        tag.append(self.utc_core.get_reg('ACQ_END_TAG_FINE'))
        return tag
-    ###########################################################################
    #======================================================================
    # Onewire thermometer and unique ID
@@ -894,6 +887,13 @@ class CFmcAdc100m:
        except CSRDeviceOperationError as e:
            raise FmcAdc100mOperationError(e)
+    # Get acquisition configuration ok flag (1=config ok)
+    def get_acq_config_ok(self):
+        try:
+            return self.fmc_adc_csr.get_field('STA', 'ACQ_CFG')
+        except CSRDeviceOperationError as e:
+            raise FmcAdc100mOperationError(e)
    #======================================================================
    # Si570 programmable oscillator