#!   /usr/bin/env   python
#    coding: utf8

# Copyright CERN, 2012
# Author: Matthieu Cattin (CERN)
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 8/5/2012


# Control and status registers of the SPEC board
FMCADC100M_CSR=['FMC ADC 100MS/s core registers',{
        'CTL':[0x00, 'Control register', {
                'FSM_CMD':[0, 'State machine commands', 0x3],
                'FMC_CLK_OE':[2, 'FMC Si570 output enable', 0x1],
                'OFFSET_DAC_CLR_N':[3, 'Offset DACs clear (Active low)', 0x1],
                'MAN_SLIP':[4, 'Manual serdes bitslip', 0x1],
                'TEST_DATA_EN':[5, 'Test data enable (address counter instead of ADC data)', 0x1],
                'TRIG_LED':[6, 'Manual control of trigger LED', 0x1],
                'ACQ_LED':[7, 'Manual control of acquisition LED', 0x1],
                'RESERVED':[8, 'Reserved', 0xFFFFFF]}],
        'STA':[0x04, 'Status register', {
                'FSM':[0, 'State machine status', 0x7],
                'SERDES_PLL':[3, 'Serdes PLL locked', 0x1],
                'SERDES_SYNCED':[4, 'Serdes synchronised', 0x1],
                'RESERVED':[5, 'Reserved', 0x7FFFFFF]}],
        'TRIG_CFG':[0x08, 'Trigger configuration', {
                'HW_TRIG_SEL':[0, 'Hardware trigger selection', 0x1],
                'HW_TRIG_POL':[1, 'Hardware trigger polarity', 0x1],
                'HW_TRIG_EN':[2, 'Hardware trigger enable', 0x1],
                'SW_TRIG_EN':[3, 'Software trigger enable', 0x1],
                'INT_TRIG_SEL':[4, 'Channel selection for internal trigger', 0x3],
                'RESERVED':[5, 'Reserved', 0x3FF],
                'INT_TRIG_THRES':[16, 'Threshold for internal trigger (two\'s compl.)', 0xFFFF]}],
        'TRIG_DLY':[0x0C, 'Trigger delay', {}],
        'SW_TRIG':[0x10, 'Software trigger', {}],
        'SHOTS':[0x14, 'Number of shots', {
                'NB':[0, 'Number of shots', 0xFFFF],
                'RESERVED':[16, 'Reserved', 0xFFFF]}],
        'TRIG_POS':[0x18, 'Trigger address register', {}],
        'SR':[0x1C, 'Sample rate', {
                'DECI':[0, 'Sample rate decimation factor', 0xFFFF],
                'RESERVED':[16, 'Reserved', 0xFFFF]}],
        'PRE_SAMPLES':[0x20, 'Pre-trigger samples', {}],
        'POST_SAMPLES':[0x24, 'Post-trigger samples', {}],
        'SAMPLES_CNT':[0x28, 'Samples counter', {}],
        'CH1_CTL':[0x2C, 'Channel 1 control register', {
                'SSR':[0, 'Solid state relays control for channel 1', 0x7F],
                'RESERVED':[7, 'Reserved', 0x1FFFFFF]}],
        'CH1_STA':[0x30, 'Channel 1 status register', {
                'VAL':[0, 'Channel 1 current ADC value', 0xFFFF],
                'RESERVED':[16, 'Reserved', 0xFFFF]}],
        'CH1_GAIN':[0x34, 'Channel 1 gain calibration register', {
                'VAL':[0, 'Gain calibration for channel 1', 0xFFFF],
                'RESERVED':[16, 'Reserved', 0xFFFF]}],
        'CH1_OFFSET':[0x38, 'Channel 1 offset calibration register', {
                'VAL':[0, 'Offset calibration for channel 1', 0xFFFF],
                'RESERVED':[16, 'Reserved', 0xFFFF]}],
        'CH2_CTL':[0x3C, 'Channel 2 control register', {
                'SSR':[0, 'Solid state relays control for channel 2', 0x7F],
                'RESERVED':[7, 'Reserved', 0x1FFFFFF]}],
        'CH2_STA':[0x40, 'Channel 2 status register', {
                'VAL':[0, 'Channel 2 current ADC value', 0xFFFF],
                'RESERVED':[16, 'Reserved', 0xFFFF]}],
        'CH2_GAIN':[0x44, 'Channel 2 gain calibration register', {
                'VAL':[0, 'Gain calibration for channel 2', 0xFFFF],
                'RESERVED':[16, 'Reserved', 0xFFFF]}],
        'CH2_OFFSET':[0x48, 'Channel 2 offset calibration register', {
                'VAL':[0, 'Offset calibration for channel 2', 0xFFFF],
                'RESERVED':[16, 'Reserved', 0xFFFF]}],
        'CH3_CTL':[0x4C, 'Channel 3 control register', {
                'SSR':[0, 'Solid state relays control for channel 3', 0x7F],
                'RESERVED':[7, 'Reserved', 0x1FFFFFF]}],
        'CH3_STA':[0x50, 'Channel 3 status register', {
                'VAL':[0, 'Channel 3 current ADC value', 0xFFFF],
                'RESERVED':[16, 'Reserved', 0xFFFF]}],
        'CH3_GAIN':[0x54, 'Channel 3 gain calibration register', {
                'VAL':[0, 'Gain calibration for channel 3', 0xFFFF],
                'RESERVED':[16, 'Reserved', 0xFFFF]}],
        'CH3_OFFSET':[0x58, 'Channel 3 offset calibration register', {
                'VAL':[0, 'Offset calibration for channel 3', 0xFFFF],
                'RESERVED':[16, 'Reserved', 0xFFFF]}],
        'CH4_CTL':[0x5C, 'Channel 4 control register', {
                'SSR':[0, 'Solid state relays control for channel 4', 0x7F],
                'RESERVED':[7, 'Reserved', 0x1FFFFFF]}],
        'CH4_STA':[0x60, 'Channel 4 status register', {
                'VAL':[0, 'Channel 4 current ADC value', 0xFFFF],
                'RESERVED':[16, 'Reserved', 0xFFFF]}],
        'CH4_GAIN':[0x64, 'Channel 4 gain calibration register', {
                'VAL':[0, 'Gain calibration for channel 4', 0xFFFF],
                'RESERVED':[16, 'Reserved', 0xFFFF]}],
        'CH4_OFFSET':[0x68, 'Channel 4 offset calibration register', {
                'VAL':[0, 'Offset calibration for channel 4', 0xFFFF],
                'RESERVED':[16, 'Reserved', 0xFFFF]}]
        }]
