#!   /usr/bin/env   python
#    coding: utf8

# Copyright CERN, 2011
# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org


# Import system modules
import sys
import time
import os

# Import specific modules
from numpy import *
from pylab import *
from ctypes import *
import fmc_adc_spec
import fmc_adc
import calibr_box
import find_usb_tty
from PAGE.Agilent33250A import *
from PAGE.SineWaveform import *

# Import common modules
import rr
from ptsexcept import *


"""
test17: Plot all channels

Note: Requires test00.py to run first to load the gateware!
"""

GN4124_CSR = 0x0

# Calibration box vendor and device IDs
BOX_USB_VENDOR_ID = 0x10c4 # Cygnal Integrated Products, Inc.
BOX_USB_DEVICE_ID = 0xea60 # CP210x Composite Device
# Agilent AWG serial access vendor and device IDs
AWG_USB_VENDOR_ID = 0x0403 # Future Technology Devices International, Ltd
AWG_USB_DEVICE_ID = 0x6001 # FT232 USB-Serial (UART) IC
RS232_BAUD = 57600
NB_CHANNELS = 4

AWG_SET_SLEEP = 0.3
SSR_SET_SLEEP = 0.05
BOX_SET_SLEEP = 0.01
DAC_SET_SLEEP = 0.01

ACQ_TIMEOUT = 10

MAX_GATEWARE_RELOAD = 10

PRE_TRIG_SAMPLES = 2000
POST_TRIG_SAMPLES = 50000
NB_SHOTS = 1

ACQ_LENGTH = 50000 # in samples
DMA_LENGTH = 4096 # in bytes

ADC_NBITS = 16 # ADC chip is 14 bits, but shifted to 16 bits in the gateware
DAC_NBITS = 16
DAC_FS = 10 # DAC full scale range is 10V


def disconnect_channels(fmc):
    for i in range(1,NB_CHANNELS+1):
        fmc.set_ssr(i, 0x00)
        time.sleep(SSR_SET_SLEEP)


def fmc_adc_init(spec, fmc):
    print('Initialise FMC board.')
    fmc.__init__(spec)
    # Reset offset DACs
    fmc.dc_offset_reset()
    # Make sure all switches are OFF
    disconnect_channels(fmc)
    # Reset offset DACs
    fmc.dc_offset_reset()
    # Set trigger
    fmc.set_soft_trig()
    # Set acquisition
    fmc.set_pre_trig_samples(PRE_TRIG_SAMPLES)
    fmc.set_post_trig_samples(POST_TRIG_SAMPLES)
    fmc.set_shots(NB_SHOTS)
    # Print configuration
    #fmc.print_adc_core_config()


def set_awg_freq(gen, sine, freq):
    sine.frequency = freq
    gen.play(sine)
    print('Sine frequency:%3.3fMHz')%(sine.frequency/1E6)
    time.sleep(AWG_SET_SLEEP)


def acquisition_all(fmc, spec_fmc):
    # Make sure no acquisition is running
    fmc.stop_acq()
    #print('Acquisition FSM state : %s') % fmc.get_acq_fsm_state()
    # Start acquisition
    fmc.start_acq()
    time.sleep(0.01)
    # Trigger
    fmc.sw_trig()
    # Wait end of acquisition
    timeout = 0
    while('IDLE' != fmc.get_acq_fsm_state()):
        #print fmc.get_acq_fsm_state()
        time.sleep(.1)
        timeout += 1
        if(ACQ_TIMEOUT < timeout):
            print('Acquisition timeout. Check that the AWG is switched ON and properly connected.')
            return 1
    # Retrieve data trough DMA
    trig_pos = fmc.get_trig_pos()
    print('Trigger position; 0x%X')%(trig_pos)
    channels_data = spec_fmc.get_data((trig_pos-(PRE_TRIG_SAMPLES*8)), (PRE_TRIG_SAMPLES+POST_TRIG_SAMPLES)*8)
    return channels_data



def plot_all(data, mean, ylimit):
    sample = arange(len(data)/4)
    clf()
    plot(sample, data[0::4], 'b', label='Channel 1')
    plot(sample, data[1::4], 'g', label='Channel 2')
    plot(sample, data[2::4], 'c', label='Channel 3')
    plot(sample, data[3::4], 'm', label='Channel 4')
    plot(sample, [mean[0]]*len(sample), 'r')
    plot(sample, [mean[1]]*len(sample), 'r')
    plot(sample, [mean[2]]*len(sample), 'r')
    plot(sample, [mean[3]]*len(sample), 'r')
    ylim(-ylimit-(ylimit/10.0), ylimit+(ylimit/10.0))
    xlim(0, len(sample))
    grid(which='both')
    legend()
    draw()
    show()
    return 0

# Converts two's complement hex to signed
def hex2signed(value):
    if(value & 0x8000):
        return -((~value & 0xFFFF) + 1)
    else:
        return value


# Converts digital value to volts
def digital2volt(value, full_scale, nb_bit):
    return float(value) * float(full_scale)/2**nb_bit


# Converts volts to digital value
def volt2digital(value, full_scale, nb_bit):
    digital = (value + full_scale/2) * 2**nb_bit/full_scale
    if(digital > 2**nb_bit - 1):
        digital = 2**nb_bit - 1
    if(digital < 0):
        digital = 0
    return int(digital)


def set_offset_dac(fmc, dac_fs, dac_nbits, channel, offset_volt):
    dac_v = offset_volt
    dac_d = volt2digital(dac_v,dac_fs,dac_nbits)
    #print('DAC value: 0x%X (%fV)')%(dac_d, dac_v)
    fmc.set_dc_offset(channel,dac_d)
    time.sleep(DAC_SET_SLEEP)


def get_mean_value(adc_fs, adc_nbits, acq):
    mean_d = []
    for channel in range(1,NB_CHANNELS+1):
        mean_d.append(mean(acq[channel-1::4]))
    mean_v = [digital2volt(item,adc_fs,adc_nbits) for item in mean_d]
    return mean_v


def main (default_directory = '.'):

    # Constants declaration
    TEST_NB = 19
    EXPECTED_BITSTREAM_TYPE = 0x1
    FMC_ADC_BITSTREAM = '../gatewares/spec_fmcadc100m14b4cha.bin'
    FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM)

    # Objects declaration
    spec = rr.Gennum() # bind to the SPEC board

    print "Loading FMC ADC gateware: %s\n" % FMC_ADC_BITSTREAM
    if(os.path.isfile(FMC_ADC_BITSTREAM)):
        spec.load_gateware(FMC_ADC_BITSTREAM)
        time.sleep(2)
    else:
        raise PtsCritical("Gateware file \"%s\" is missing, test stopped." % FMC_ADC_BITSTREAM)

    carrier = fmc_adc_spec.CFmcAdc100mSpec(spec, EXPECTED_BITSTREAM_TYPE)
    fmc = fmc_adc.CFmcAdc100m(spec)
    usb_tty = find_usb_tty.CttyUSB()
    awg_tty = usb_tty.find_usb_tty(AWG_USB_VENDOR_ID, AWG_USB_DEVICE_ID)
    box_tty = usb_tty.find_usb_tty(BOX_USB_VENDOR_ID, BOX_USB_DEVICE_ID)
    gen = Agilent33250A(device=awg_tty[0], bauds=RS232_BAUD)
    sine = SineWaveform()
    box = calibr_box.CCalibr_box(box_tty[0])

    # Work-around to make dma work with sdb gateware
    #carrier.gnum.set_local_bus_freq(200)
    print "GN4124 local bus freq: ", carrier.gnum.get_local_bus_freq()

    # Enable "DMA finished" IRQ
    carrier.enable_dma_done_irq()

    # Initialise fmc adc
    fmc_adc_init(spec, fmc)

    # Use test data instead of data from ADC
    #fmc.test_data_en()

    # Use data pattern instead of ADC data
    #fmc.testpat_en(0x2000)

    # Connect to AWG
    #gen.connect()

    # Switch AWG output OFF
    #gen.output = False

    # Measure FMC and carrier temperature
    print('SPEC temperature: %3.3f°C') % carrier.get_temp()
    print('FMC temperature : %3.3f°C') % fmc.get_temp()

    # Open all switches, reset offset DAC to mid-scale (0V)
    for channel in range(1,NB_CHANNELS+1):
        fmc.set_input_range(channel, 'OPEN')
        fmc.set_input_term(channel, 'OFF')
    fmc.dc_offset_reset()


    # ADC full scale is 100mV
    select = raw_input('Select input range [1=10V, 2=1V, 3=100mV]:')
    if('1' == select):
        print('10V input range selected')
        ADC_FS = 10.0
        in_range = '10V'
    elif('2' == select):
        print('1V input range selected')
        ADC_FS = 1.0
        in_range = '1V'
    elif('3' == select):
        print('100mV input range selected')
        ADC_FS = 0.1
        in_range = '100mV'
    else:
        print('10V input range selected')
        ADC_FS = 10.0
        in_range = '10V'

    # Set calibration box to AWG
    box.select_output_ch(1)
    time.sleep(BOX_SET_SLEEP)

    # All offset DACs to 0V
    for channel in range(1,NB_CHANNELS+1):
        set_offset_dac(fmc, DAC_FS, DAC_NBITS, channel, 0.0)

    # Set channel input range
    for channel in range(1,NB_CHANNELS+1):
        fmc.set_input_range(channel, in_range)
        time.sleep(SSR_SET_SLEEP)

    # Measures value on each channel
    acq_d = acquisition_all(fmc, carrier)
    acq_d = [hex2signed(item) for item in acq_d]
    acq_v = [digital2volt(item,ADC_FS,ADC_NBITS) for item in acq_d]
    mean_v = get_mean_value(ADC_FS, ADC_NBITS, acq_d)
    plot_all(acq_v, mean_v, ADC_FS/2.0)


    # Close AWG
    #gen.close()

    # Check if an error occured during frequency response test
    #if(error != 0):
    #    raise PtsError('An error occured during frequency response test, check log for details.')


if __name__ == '__main__' :
    main()
