The FMCADC100M14b4cha has a HPC (High Pin-Count connector) whereas on the SPEC there is a LPC (Low Pin-Count connector)?
The FMCADC100M14b4cha actually has a HPC connector mounted (indeed that is in the BOM). However, none of the HPC signals is used in any current applications, so actually an LPC could have been mounted instead.
The clock for the ADC is generated on the mezzanine card itself (by a programmable Si570 oscillator) and this clock is output from the mezzanine to the carrier on an LPC pin. We had foreseen that some applications may need a clock coming from the carrier going into the mezzanine. In this case one must use a HPC connector as in the FMC standard there are no dedicated clock pins in that direction on an LPC connector (we believe this is a weak point in the FMC standard). In this case one has to remove two capacitors (C22, C23) and move them to the locations C24 and C25 (see schematics V5-0, page 5). We have never used this and commercial FMCADC100M14b4cha mezzanine are all sold with the clock generated on the FMC mezzanine. Furthermore indeed the SPEC carrier cannot generate a clock to the mezzanine as it uses an LPC connector
For White Rabbit, where we actually do generate a clock on the carrier and need to sample to that very precise clock, we actually program the Si570 oscillator (see schematics V5-0, page 4) so that it follows and locks to the White Rabbit clock on the carrier. We started in October 2012 the ADC FMC board clock synchronization mechanism task that will do precisely this. There will some code running in the Xilinx that will basically implement a Phase-locked loop that controls continuously the Si570 to track the White Rabbit clock.
The above should also explain the somewhat cryptic text in the specification: "FMC to carrier interface FMC high pin count connector (HPC only used if external clock is selected)"
I supposed that the external clock was entering the FMC directly with a Lemo00 connector?
That is wrong. It is not foreseen to have an external clock input on the mezzanine card. There is only place for five Lemo00 connectors and these are used as four signal inputs and one external trigger input.
The schematics (V5 and V6) says that "VADJ must be set to 2.5V.", can't the fmc-adc work with VADJ = 3.3V?
The fmc-adc mezzanine will likely work on a carrier setting VADJ at 3.3V (not tested).
This comment is possibly outdated and could be replaced by a range of allowed values.
The full comment in the schematics (p.3) is:
- VADJ must be set to 2.5V.
- 2.5V has been choosen because:
- there is no need of level matching for DAC SPI interface
- FMC board could be tested with Xilinx kit, where VADJ is fixed to 2.5V
So if you want to use another value of Vadj, this has to be studied seriously.
Erik van der Bij, Matthieu Cattin - March 2020