FMC ADC 100M 14B 4CHA Hardware
Overview
This project contains the information about the hardware for the fmc-adc-100m14b4cha project.
[fmc-adc board version 3 front and top view.]
Specifications
Parameter | Value |
max. sample rate | 105 MSPS |
analog bandwidth | 30 MHz. DC-coupled (40 MHz possible by changing eight capacitors) |
bits/sample | 14 bit |
ENOB | 11, 11.5, 11.7 bit (@ /-50mV,/-0.5V, +/-5V range) |
channels | 4 |
connectors | 4 x LEMO 00 for signals, 1 x LEMO 00 for trigger |
input impedance | 1 kOhm / 50 Ohm - software selectable |
gain steps | /-50 mV,/-0.5 V, +/-5 V for full scale |
offset correction range | +/- 5 V for every input voltage range |
max. gain error | +/- 1 % |
SNR | 67.7 dB, 70.8 dB, 72.2 dB (@ /-50mV,/-0.5V, +/-5V range) |
FMC to carrier interface | FMC high pin count connector (HPC only used if external clock is selected) |
ADC interface | Serial LVDS, 2 pairs for each channel |
Clock source | Internal: from programmable on-board oscillator. External: from dedicated FMC connector pins (HPC) when changing two capacitors. |
Versions
- Official production documentation (schematics, PCB, etc.): EDMS: EDA-02063
- Currently supported version: FMCADC100M14b4cha V5 - EDA-02063-V5-0
Documentation
Support
We offer the following sources of support:
- Frequently Asked Questions
- Mailing list fmc-adc-100m14b4cha@ohwr.org and its archive.
Please** read the documentation and then the FAQ before asking for support on the mailing list.
Contacts
Maintainers
- Matthieu Cattin - CERN
People involved
- "Maciej Fimiarz" - ex-CERN
- Erik Van der Bij - CERN
Status
Date | Event |
22-01-2010 | FmcAdc100M14b4cha upgrade. Design revised and modified, better parameters expected. |
10-02-2010 | New design made with 3 input ranges and programmable offset. |
04-03-2010 | Improvements made, responding to V1 design review. |
24-03-2010 | Design review of PCB layout V1 done. |
09-06-2010 | 3 assembled boards received. |
12-07-2010 | One board plugged in on Xilinx development kit and powered. Debugging start. |
30-07-2010 | ENOB & SNR measured: >11 bits in all ranges. |
08-09-2010 | Issue with linearity in the 30-90 kHz region caused by offset compensation circuit being investigated. |
29-09-2010 | Updates to PCB made (EDA-02063-V2). Ten boards ordered. Designer left CERN. |
07-01-2011 | Ten V2 boards arrived. |
04-07-2011 | V3 reviewed. V3 review. 3 prototypes will be built. V3 changelog. |
01-08-2011 | Price Enquiry sent out for first Open Hardware production. |
15-09-2011 | V4 design made. Corrected some textual problems and one BOM item order number. |
20-09-2011 | Order for 40 cards placed with INCAA Computers (V5). Delivery in January 2012. |
20-12-2011 | Measured bandwidth is 30 MHz. 40 MHz bandwidth is possible by changing 2 capacitors per channel. |
04-04-2012 | First production received: 40 V5 cards produced by INCAA Computers. |
24-03-2014 | Cards deployed in CERN's accelerator complex. Start of development to deployement: 4.5 year. |
22-04-2014 | CERN ordered 100 boards (V5-0) for delivery by 18/7/14 (20) and 19/9/14 (80). |
18-07-2014 | Received 20 pre-series boards. |
Matthieu Cattin - August 2014