FMC ADC 100M 14b 4cha - Hardware issueshttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues2022-06-15T09:20:42Zhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/68V6-0 - Create V6-1 EDMS files with capacitor changes and L8 removed.2022-06-15T09:20:42ZErik van der BijV6-0 - Create V6-1 EDMS files with capacitor changes and L8 removed.I wrote to the Design office on 14/6/22:
> We found some problems on our FMC-ADC100M cards, the EDA-02063-V6-0.
> https://edms.cern.ch/nav/EDA-02063-V6-0
>
> It will require changes of some of the components (16 capacitors, one inductor), without changing the PCB.
> The required changes are described at
> https://ohwr.org/project/fmc-adc-100m14b4cha-hw/wikis/v6_0_to_v6_1
>
> We should document those changes so that the latest schematics are correct.
> Although the problem is also present in earlier PCB versions, I think it is sufficient to make a V6-1 only.
>
> Can you update V6-0 into a V6-1, or do you have other ways to treat cases like this?
Reply:
> I just created the work order for this design change. I confirm it will be V6-1.
> If you list the old versions having the same problem, I will create a non-conformity dedicated for each version/execution.
> We will then know in case of new request for the old versions that we have to make design change before production.V6.12022-08-31Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/67Document 4th input voltage range, +/-1V?2022-06-14T09:17:06ZErik van der BijDocument 4th input voltage range, +/-1V?See this issue in the "top-level" project:
https://ohwr.org/project/fmc-adc-100m14b4cha/issues/10https://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/66V5, V6 - Reliability2022-06-14T12:27:52ZErik van der BijV5, V6 - ReliabilityChristos’ utility shows that 16 out of the 18 0603-sized X5R 10uF/6.3V capacitors operate at 6.0V. See the attached spreadsheet.
These should be changed by higher-rated voltage ones to increase the reliability as they are not overrated according to the usual guidelines.
The 0603 X5R 6.3V rated capacitors should be replaced with C0G 16V rated capacitors *if available* in the same package. C0G capacitors are more expensive, but show a good capacitance stability over temperature
and when operating close to voltage rating value.
[EDA-02063-V6-0.ods](/uploads/f6adbf23c693bd2d6df91bd553058618/EDA-02063-V6-0.ods)V6.1https://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/65V5, V6 - 1.8V low. May result in spikes or noise2022-06-14T12:27:31ZErik van der BijV5, V6 - 1.8V low. May result in spikes or noiseIt seems that the 1.8V supply to the ADC is low which may show up as spikes or noise in the measurements.
1. The 10uF capacitor may not have that value (capacitance is lower when used below the nominal voltage), maybe less than 4uF.
2. The inductor in the path for the analogue supply removes 88mV.
The report [2] from HT-859 [3] describes that the 1.8V power supply is on the low side, notably the analogue supply.
The suggestions are to implement any one of these two:
- Remove L8 and short it.
- Gains 88mV on ADC_ANALOG (1.8V)
- Add another 10uF capacitor in parallel with C54 (10uF, 0603)
- To verify with the assembly workshop if this is feasible
Removing L8 may influence the noise level to the ADC which is an important parameter.
I suggest that even before applying this change, the SNR/ENOB (effective number of bits) should be measured, similar to those done before [4,5].
The report suggests that only adding an additional capacitor is enough to solve the problem:
“The voltage output of the LDO became insensible to temperature changes and increased the voltage to its nominal value.”
and puts this change on the same level as removing L8:
“Removing one inductor also gave the same result.”
My preference:
• Check if just adding another C in parallel with C54 is “good enough” (after all, hundreds of cards have been installed and are functional).
• If so: do this modification on the cards that stock and replace “à fur et à mésure”.
[1] https://issues.cern.ch/browse/INST-3767?focusedCommentId=382662&page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel#comment-382662
[2] https://issues.cern.ch/secure/attachment/72136/failure%20analysis%20report-1.pdf
[3] https://issues.cern.ch/browse/HT-859
[4] https://ohwr.org/project/fmc-adc-100m14b4cha-hw/wikis/l1_alternative_measurements
[5] https://ohwr.org/project/fmc-adc-100m14b4cha/wikis/home#specificationsV6.1https://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/64V5 - Replace LEMO connectors by backwards compatible type2019-12-03T14:14:42ZErik van der BijV5 - Replace LEMO connectors by backwards compatible typeWhen going from V6 to V5 the LEMO connector type has been changed from EPL to EPK.
The EPK type is compatible to the EPL-type used before.
**V6**
- https://edms.cern.ch/file/2258651/1/EDA-02063-V6-0_pcb-mat.pdf
- J5 EPK.00.250.NTN (09.46.11.180.6)
- https://www.lemo.com/pdf/EPK.00.250.NTN.pdf
**V5**
- https://edms.cern.ch/file/1165461/1/EDA-02063-V5-0_pcb-mat.pdf
- J1-J5 EPL.00.250.NTN (09.46.11.180.6)
- https://www.lemo.com/pdf/EPL.00.250.NTN.pdf
The CERN SCEM item number is the same and now the Stores catalogue shows the one used in V6: EPK.00.250.NTN
https://edh.cern.ch/edhcat/Browser?command=searchItems&scem=09.46.11.180.6#
The EPK has liberated some space in the housing and makes it looks like that the corner pins are on some feet.
The connector body therefore no longer touches the board, and prevents short circuits on some designs. EDA-02063 may use both types.
![LEMO](/uploads/3664a5b97b4ab4446e235cbfa34c5a24/LEMO.png)V6.0Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/63V5 - make C41 "do not mount"2019-11-08T18:09:27ZErik van der BijV5 - make C41 "do not mount"I recommend we make C41 "do not mount", because removing it stopped the instability in the voltage regulation feed back loop. However other layout changes may requires some capacitance to be fitted. The final layout will need to be checked for control loop stability to answer this question.V6.0Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/62V5 - Obsolete L1: CTX10-1A-R, Dual Winding Shielded Power Inductor/Transformer2019-11-08T18:18:04ZErik van der BijV5 - Obsolete L1: CTX10-1A-R, Dual Winding Shielded Power Inductor/TransformerSee https://forums.ohwr.org/t/ctx10-1a-r-has-been-discontinued-by-eaton-cooper-bussmann/848245 for the proposal of an alternative type.V6.0Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/1V5 - Obsolete inductor L1: CTX10-1A-R2019-08-05T11:20:36ZErik van der BijV5 - Obsolete inductor L1: CTX10-1A-RProducer of cards mentioned that the inductor L1, CTX10-1A-R is
obsolete.
This is a transformer used to generate the negative supply voltages.
For the 2018 production the supplier managed to buy the component via a
broker.https://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/2V5 - Improving temperature compensation2019-08-05T09:42:09ZErik van der BijV5 - Improving temperature compensationSundance suggested:
The graphs for both ADC and DAC gains are all close to a straight a
line, so a simple 2 point temperature correction calibration would
reduce these errors by at least an order of magnitude.
Consider the above suggestion for a straight line software gain
correction, instead of the existing single point gain correction. This
requires no hardware changes, and the driver modifications could handle
boards calibrated with either a single or double point gain correction.
Please refer to the measurements reports
https://www.ohwr.org/project/fmc-adc-100m14b4cha-hw/wikis/Documents/2017-and-2018-Integration-and-Measurement-resultsDimitris LampridisDimitris Lampridishttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/3V5 - Gain error drift caused by MOS relays varying resistance.2019-10-08T15:14:45ZErik van der BijV5 - Gain error drift caused by MOS relays varying resistance.Sundance suggested a possible reason for the (already low enough)
temperature drift. This suggestion may need to be worked out and may be
used in a future version of the design.
I kept thinking that the gain error drifts for BOTH ADC and DAC are an
order of magnitude lower on the 1V0 range, but also that the ADC and DAC
error drifts are almost identical.
Logically this means the drift must be in a component which is common to
both ADC and DAC, and which is part of the gain setting circuit.
A look at the schematic and the obvious candidate is the photomos
relays, which are AQY221N3M.
The data sheet for these says the on resistance is typically 5.5R,
however there is a temperature dependency graph, which shows the on
resistance varies from about 4R to 7.5R over the range 0 to 70
degrees.
Given the low impedance of the rest of this part of the circuit, that
drift easily accounts for the measured 1% error drifts, and will
completely dominate any drift in the precision resistors.
Panasonic make a lower resistance version AQY221R2M with resistance
drift from about 0.5R to 1.5R (it is a small graph) over 0 to 70
degrees, but it has much higher capacitance at 14pF (instead of 1.1pF),
which will probably effect the high frequency response.
While this might be worth a simple trial, the loss of high frequency
response may make it unusable, even though I am fairly sure it would
greatly improve the ADC and DAC gain temperature drift.
Best regards
Steve
Please refer to the measurements reports
https://www.ohwr.org/project/fmc-adc-100m14b4cha-hw/wikis/Documents/2017-and-2018-Integration-and-Measurement-resultshttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/4EEPROM type not compatible with VITA 57.12019-10-08T15:31:25ZDimitris LampridisEEPROM type not compatible with VITA 57.1In order to comply with VITA 57.1 standard, the FMC EEPROM needs to be
changed to 24C02.https://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/5V5 - differential impedances not precise2019-10-08T15:15:36ZErik van der BijV5 - differential impedances not preciseWhen calculating the impedance of the above design I noticed that on the
top, layer 3 and bottom layers that there appears to be paired tracks in
which don’t match the spacing specified on the supplied construction
(8.2 thou track & 5 thou spacing). Please could you take a look at
Impedance(top).PNG, Impedance(layer 3).PNG, Impedance(bottom).PNG
attached and confirm if the highlighted tracks are the paired tracks in
which are to be impedance controlled?
Also the construction states that the impedance required is to be 100
Ohms however if we are to followed the supplied files our software is
calculating that the impedance would be 89.71 Ohms on the top and bottom
track layers and 79.16 Ohms on layer 3. Our software is calculating that
in order to meet the 100 ohms impedance required that on the top and
bottom track layers we would need to change the finished track widths
from 8.2 thou tracking with 5 thou spacing to 7.1 thou tracking with 6.1
thou spacing and on layer 3 we need to change the 8.2 thou tracking with
5 thou spacing to 5.65 thou tracking with 7.55 thou spacing. Please
could you verify if we are ok to change these track widths in order to
meet the 100 Ohms impedance requirement?
See attached images.
Reported by Graeme Parker \<graeme.p@sundance.com\> on 6/12/17.
- Erik replied for production: "These lines are not very critical.
Please produce the cards using the original Gerber files. There is
no need to modify the trace width".
### Files
* [Impedance__bottom_.png](/uploads/4fafa5953c465ee6fa05cde21951e724/Impedance__bottom_.png)
* [Impedance__top_.png](/uploads/037ce1bc49d668fe7ec5eebafb8d2ac3/Impedance__top_.png)
* [Impedance__Layer3_.png](/uploads/7f80f8d1cb5bf77d1cccf042ef8e2b7e/Impedance__Layer3_.png)https://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/6V5 - T1,T2, BOM description is wrong2019-11-08T18:40:17ZErik van der BijV5 - T1,T2, BOM description is wrongThe BOM at
https://edms.cern.ch/ui/file/1165461/1/EDA-02063-V5-0_pcb-mat.pdf
reads:
T1,T2 2 **50V 200mA** N-Channel Enhancement Mode Field-Effect Transistor
BSH103 NXP SEMICONDUCTORS BSH103 SOT23-3
The description of **50V 200mA** is wrong.
The datasheet at
https://assets.nexperia.com/documents/data-sheet/BSH103.pdf (This NXP
part is moved to Nexperia)
shows **30V 0.85A**.
- Correct description of library item BSH103 to show 30V 0.85A instead
of 50V, 200mA.
- Change NXP SEMICONDUCTORS to Nexperia (see cover letter on the
datasheet)
*Problem found by Seven Solutions, during price enquiry for production.*V6.0Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/7V5 - Wrong comment on Vadj in schematics2019-10-08T15:08:15ZProjectsV5 - Wrong comment on Vadj in schematicsOn the power supplies schematics page, a comment says "VADJ must be set
to 2.5V.".
But the fmc-adc mezzanine will work with other Vadj voltages (e.g 3.3V).
\=\> Define the allowed Vadj range for fmc-adc.https://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/8V5 - Specify Phillips screws instead of Hexalobular type2019-11-08T18:38:57ZErik van der BijV5 - Specify Phillips screws instead of Hexalobular typeThe [mechanical
BOM](https://edms.cern.ch/file/1165461/1/EDA-02063-V5-0_arrangement-mat.pdf)
specifies "Hexalobular Pan Head Screws".
(BN 5687 ISO 14583 - Hexalobular Pan Head Screws - Fully Threaded -
Stainless Steel A2 M2.5 - L=6mm BOSSARD - 3061597)
However, the Xtech and ELMA FMC front-panel kits both contain Phillips
screws. Also it is more practical to use Phillips screws.
Improve BOM. Copy info from
[FMC\_Delay\_1ns\_4Cha](https://edms.cern.ch/file/1382769/1/EDA-02267-V6-0_arrangement-mat.pdf)
BOM. And improve as those specify that the screws are in the kit, but do
not specify the type at all (just
[pan-head](http://en.wikipedia.org/wikis/Screw#mediaviewer/file:screw_head_types.svg)
(image A).V6.0Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/9V5 - Solder leaks through non-capped area under ADC component2022-03-21T08:55:58ZErik van der BijV5 - Solder leaks through non-capped area under ADC componentAs the holes in the copper/gold-plated area under the ADC component are
not capped and filled, solder is leaking through it.
Visually it is not appealing (see attached file), while it may cause
(unlikely though) that the connection between the copper plate under the
DAC IC and the PCB may not be made in the best way as solder may have
leaked away.
It was suggested by a production company to use Capped and Filled vias
in this area. This is actually done on the Fine Delay card too
(capped-and-filled under 5 ICs, no solder mask over the areas).
Note that cap-and-fill is very expensive (\> 50 CHF/board?) and may well
be overkill in this case. A soldermask over the area will fill the holes
enough to prevent the solder from leaking through, but may slightly
increase the temperature.
See also:
- https://www.ohwr.org/work_packages/459 (ADC)
- https://www.ohwr.org/work_packages/580 (Fine Delay)
### Files
* [photo.JPG](/uploads/340cc6c7a2c47c77797be390d5041a3c/photo.JPG)V6.0Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/10V5 - Replace FMC front panel kit2019-11-08T18:33:11ZProjectsV5 - Replace FMC front panel kitReplace the Xtech FMC front panel kit, the two spacers and the four
hexalobular screws by the following ELMA kit reference:
21M280-2
[ELMA 21M280-2 datasheet](http://www.elma.com/-/media/product-files/enclosures-and-components/front-panels-and-digital-printing/files/ch15-datasheet-fmcmezzaninefrontpanels-e.ashx) - see section "Scope of delivery" as the table in the datasheet is not complete.
The ELMA 21M280-2 kit contains:
- 1 FMC front panel
- 1 O-ring
- 2 10mm spacers
- 4 M2.5x6mm screws
---
V6.0Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/11V5 - Add soldermask both sides near standoff2022-03-21T08:55:35ZErik van der BijV5 - Add soldermask both sides near standoffIn the corner near standoff B4 there is no soldermask on copper areas on
both sides of the board. The idea was that this should improve the
cooling in this area that gets hot because of the regulator in this
corner. However, as there is no soldermask, the solder for the
components is leaking out (see attached images) which can create
problems.
As the surface is so small anyway, we believe it is better to add the
soldermask.
- Add soldermask on both sides near the B4 standoff to improve
solderability.
### Files
* [IMG_1176.JPG](/uploads/985199534940fcc16f4837de812066ad/IMG_1176.JPG)
* [IMG_1180.JPG](/uploads/ef42e4d7f10e0f5552d0c5fbca300852/IMG_1180.JPG)V6.0Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/12V5 - Mount LPC connector instead of HPC2019-10-08T15:14:12ZErik van der BijV5 - Mount LPC connector instead of HPC- Mount a Low Pin Count (LCP) connector instead of a High Pin Count
(HPC). This will ease assembly and notably will make a visual check
of the soldering of the relevant signals possible.
- Keep the layout the same, so that in special applications still a
HPC can be mounted. Note that in that case also two capacitors must
be moved to select this external clock.
- May be a EDA-02063-V5-1 as the PCB will stay the same.
Background
The HPC part of the connector is uniquely used when feeding an external
clock signal to the FMC mezzanine. However, this possibility has not
been used in CERN's applications. In case the sampling needs to be
synchronous to an external clock, it will be possible to synchronise the
local Si570 oscillator to this external clock by the controlling FPGA on
the carrier card.
Therefore the external clock signal will never be fed to the mezzanine
card and the use of the HPC connector is superfluous. During the first
series production we have seen assembly problems on the outer row of the
HPC connector that could not be detected by the test program as they are
not used. The inner pins are not visible as they are hidden by two rows
of these unused signals.https://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/13V5 - update data for Si5702019-11-08T18:28:31ZErik van der BijV5 - update data for Si570In the BOM the Silicon Labs 570BBC000121DG is described as a generic
component without the specific startup frequency mentioned:
- Description: 10-280MHz 3.3V ±20ppm LVDS Any-Rate I2C Programmable XO
Oscillator Si570 Serie
- Val\&Device: 10-280MHz -- to change to 100.000000 MHz
- Manufacturer P/N: SILICON LABS 570BBC000121DG
Correct the BOM to include the startup frequency of 100.000000 MHz. This
likely needs an update of the symbol in the schematics.V6.0Erik van der BijErik van der Bij