FMC ADC 100M 14b 4cha - Hardware issueshttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues2019-12-03T14:14:42Zhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/64V5 - Replace LEMO connectors by backwards compatible type2019-12-03T14:14:42ZErik van der BijV5 - Replace LEMO connectors by backwards compatible typeWhen going from V6 to V5 the LEMO connector type has been changed from EPL to EPK.
The EPK type is compatible to the EPL-type used before.
**V6**
- https://edms.cern.ch/file/2258651/1/EDA-02063-V6-0_pcb-mat.pdf
- J5 EPK.00.250.NTN (09.46.11.180.6)
- https://www.lemo.com/pdf/EPK.00.250.NTN.pdf
**V5**
- https://edms.cern.ch/file/1165461/1/EDA-02063-V5-0_pcb-mat.pdf
- J1-J5 EPL.00.250.NTN (09.46.11.180.6)
- https://www.lemo.com/pdf/EPL.00.250.NTN.pdf
The CERN SCEM item number is the same and now the Stores catalogue shows the one used in V6: EPK.00.250.NTN
https://edh.cern.ch/edhcat/Browser?command=searchItems&scem=09.46.11.180.6#
The EPK has liberated some space in the housing and makes it looks like that the corner pins are on some feet.
The connector body therefore no longer touches the board, and prevents short circuits on some designs. EDA-02063 may use both types.
![LEMO](/uploads/3664a5b97b4ab4446e235cbfa34c5a24/LEMO.png)V6.0Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/45Add LHC equipment name "CFFIA" on front-panel and PCB2019-02-12T11:14:54ZErik van der BijAdd LHC equipment name "CFFIA" on front-panel and PCBThis will help in stock management.Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/42Mounting holes for SMC connectors seem too large, but aren't2019-02-12T11:14:51ZErik van der BijMounting holes for SMC connectors seem too large, but aren'tThe 5 mounting holes for soldering the SMC connectors seem too large.
There is quite some space and they can move a lot when not yet
soldered.
The hole size according to the PCB design are 1.7 mm (x4) and 1.2 mm
(x1), which is precisely the same according to the datasheet of the
connector (of 2 brands). So there should be no problem. But it still may
be difficult to get the front-panel assembled later.
Verify with DEM quality office.
Maybe add assembly instructions (mount front-panel before soldering)?Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/31V2 - Add CERN OHL licence2019-02-12T11:14:44ZProjectsV2 - Add CERN OHL licence1\) Add the following to the schematics:
Copyright CERN 2011.
This documentation describes Open Hardware and is licensed under the
CERN OHL v. 1.0.
You may redistribute and modify this documentation under the terms of
the CERN OHL v.1.0. (insert link). This documentation is distributed
WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY,
SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see
the CERN OHL v.1.0 for applicable conditions.
2\) Add the following to the layout:
Licensed under CERN OHL v.1.0
3\) Remove the CERN logo from the layout.
4\) Add the required files to the repo.Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/30V2 - Replace input connectors by LEMO ?2019-02-12T11:14:43ZProjectsV2 - Replace input connectors by LEMO ?https://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/29V2 - Change front panel legend "PWR"2019-02-12T11:14:42ZProjectsV2 - Change front panel legend "PWR"Replace the front panel legend "PWR" by something like "ACQ" (to
indicate that acquisition is in progress).https://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/28V2 - Connect front panel directly to GND2019-02-12T11:14:42ZProjectsV2 - Connect front panel directly to GNDhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/27V2 - Connect Si570 I2C pull-ups directly to 3P3V2019-02-12T11:14:41ZProjectsV2 - Connect Si570 I2C pull-ups directly to 3P3Vhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/26V2 - Add a "-" between Fmc and Adc on the front panel2019-02-12T11:14:41ZProjectsV2 - Add a "-" between Fmc and Adc on the front panelhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/24V3 - Change license to OHL V1.12019-02-12T11:14:39ZProjectsV3 - Change license to OHL V1.1Change license to OHL V1.1 on the schematics and silkscreen.
Remove CERN logo form silkscreen.Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/22V4 - May possibly reduce crosstalk by removing shields or adding vias2019-11-08T18:20:33ZErik van der BijV4 - May possibly reduce crosstalk by removing shields or adding viasOn layer 1 of the PCB, near the ADC, there are copper islands to
separate the input signals. By removing them (scratching away) one may
try to see if these islands are not counterproductive.V6.0Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/18V5 - Line spacing diff lines not precise2019-10-08T15:12:08ZErik van der BijV5 - Line spacing diff lines not preciseProducer found some inconsitencies in line spacing of differential
lines.
At layer 3 differential impedance is asked for certain tracks.
Theoretically 0.208mm track and 0.127 spacing is mentioned. However, we
see that certain spacings are not at all 0.127mm. Other pairs have
partially at 0.127 spacing, but later they'll continue at 0.15mm or
0.17mm.
- Visual check shows no serious problems, so V5 is OK for production
(EB).
- Verify if needs to be corrected in V6.
### Files
* [snap03.bmp](/uploads/8822d3375c61544aae67b08a2e6653d9/snap03.bmp)
* [snap04.bmp](/uploads/0f10605ec5fbfa95f1c189ee47e1c2bb/snap04.bmp)
* [snap06.bmp](/uploads/3776d95561eeab4eb750938f86ad1d6c/snap06.bmp)https://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/13V5 - update data for Si5702019-11-08T18:28:31ZErik van der BijV5 - update data for Si570In the BOM the Silicon Labs 570BBC000121DG is described as a generic
component without the specific startup frequency mentioned:
- Description: 10-280MHz 3.3V ±20ppm LVDS Any-Rate I2C Programmable XO
Oscillator Si570 Serie
- Val\&Device: 10-280MHz -- to change to 100.000000 MHz
- Manufacturer P/N: SILICON LABS 570BBC000121DG
Correct the BOM to include the startup frequency of 100.000000 MHz. This
likely needs an update of the symbol in the schematics.V6.0Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/12V5 - Mount LPC connector instead of HPC2019-10-08T15:14:12ZErik van der BijV5 - Mount LPC connector instead of HPC- Mount a Low Pin Count (LCP) connector instead of a High Pin Count
(HPC). This will ease assembly and notably will make a visual check
of the soldering of the relevant signals possible.
- Keep the layout the same, so that in special applications still a
HPC can be mounted. Note that in that case also two capacitors must
be moved to select this external clock.
- May be a EDA-02063-V5-1 as the PCB will stay the same.
Background
The HPC part of the connector is uniquely used when feeding an external
clock signal to the FMC mezzanine. However, this possibility has not
been used in CERN's applications. In case the sampling needs to be
synchronous to an external clock, it will be possible to synchronise the
local Si570 oscillator to this external clock by the controlling FPGA on
the carrier card.
Therefore the external clock signal will never be fed to the mezzanine
card and the use of the HPC connector is superfluous. During the first
series production we have seen assembly problems on the outer row of the
HPC connector that could not be detected by the test program as they are
not used. The inner pins are not visible as they are hidden by two rows
of these unused signals.https://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/10V5 - Replace FMC front panel kit2019-11-08T18:33:11ZProjectsV5 - Replace FMC front panel kitReplace the Xtech FMC front panel kit, the two spacers and the four
hexalobular screws by the following ELMA kit reference:
21M280-2
[ELMA 21M280-2 datasheet](http://www.elma.com/-/media/product-files/enclosures-and-components/front-panels-and-digital-printing/files/ch15-datasheet-fmcmezzaninefrontpanels-e.ashx) - see section "Scope of delivery" as the table in the datasheet is not complete.
The ELMA 21M280-2 kit contains:
- 1 FMC front panel
- 1 O-ring
- 2 10mm spacers
- 4 M2.5x6mm screws
---
V6.0Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/9V5 - Solder leaks through non-capped area under ADC component2022-03-21T08:55:58ZErik van der BijV5 - Solder leaks through non-capped area under ADC componentAs the holes in the copper/gold-plated area under the ADC component are
not capped and filled, solder is leaking through it.
Visually it is not appealing (see attached file), while it may cause
(unlikely though) that the connection between the copper plate under the
DAC IC and the PCB may not be made in the best way as solder may have
leaked away.
It was suggested by a production company to use Capped and Filled vias
in this area. This is actually done on the Fine Delay card too
(capped-and-filled under 5 ICs, no solder mask over the areas).
Note that cap-and-fill is very expensive (\> 50 CHF/board?) and may well
be overkill in this case. A soldermask over the area will fill the holes
enough to prevent the solder from leaking through, but may slightly
increase the temperature.
See also:
- https://www.ohwr.org/work_packages/459 (ADC)
- https://www.ohwr.org/work_packages/580 (Fine Delay)
### Files
* [photo.JPG](/uploads/340cc6c7a2c47c77797be390d5041a3c/photo.JPG)V6.0Erik van der BijErik van der Bijhttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/7V5 - Wrong comment on Vadj in schematics2019-10-08T15:08:15ZProjectsV5 - Wrong comment on Vadj in schematicsOn the power supplies schematics page, a comment says "VADJ must be set
to 2.5V.".
But the fmc-adc mezzanine will work with other Vadj voltages (e.g 3.3V).
\=\> Define the allowed Vadj range for fmc-adc.https://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/5V5 - differential impedances not precise2019-10-08T15:15:36ZErik van der BijV5 - differential impedances not preciseWhen calculating the impedance of the above design I noticed that on the
top, layer 3 and bottom layers that there appears to be paired tracks in
which don’t match the spacing specified on the supplied construction
(8.2 thou track & 5 thou spacing). Please could you take a look at
Impedance(top).PNG, Impedance(layer 3).PNG, Impedance(bottom).PNG
attached and confirm if the highlighted tracks are the paired tracks in
which are to be impedance controlled?
Also the construction states that the impedance required is to be 100
Ohms however if we are to followed the supplied files our software is
calculating that the impedance would be 89.71 Ohms on the top and bottom
track layers and 79.16 Ohms on layer 3. Our software is calculating that
in order to meet the 100 ohms impedance required that on the top and
bottom track layers we would need to change the finished track widths
from 8.2 thou tracking with 5 thou spacing to 7.1 thou tracking with 6.1
thou spacing and on layer 3 we need to change the 8.2 thou tracking with
5 thou spacing to 5.65 thou tracking with 7.55 thou spacing. Please
could you verify if we are ok to change these track widths in order to
meet the 100 Ohms impedance requirement?
See attached images.
Reported by Graeme Parker \<graeme.p@sundance.com\> on 6/12/17.
- Erik replied for production: "These lines are not very critical.
Please produce the cards using the original Gerber files. There is
no need to modify the trace width".
### Files
* [Impedance__bottom_.png](/uploads/4fafa5953c465ee6fa05cde21951e724/Impedance__bottom_.png)
* [Impedance__top_.png](/uploads/037ce1bc49d668fe7ec5eebafb8d2ac3/Impedance__top_.png)
* [Impedance__Layer3_.png](/uploads/7f80f8d1cb5bf77d1cccf042ef8e2b7e/Impedance__Layer3_.png)https://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/3V5 - Gain error drift caused by MOS relays varying resistance.2019-10-08T15:14:45ZErik van der BijV5 - Gain error drift caused by MOS relays varying resistance.Sundance suggested a possible reason for the (already low enough)
temperature drift. This suggestion may need to be worked out and may be
used in a future version of the design.
I kept thinking that the gain error drifts for BOTH ADC and DAC are an
order of magnitude lower on the 1V0 range, but also that the ADC and DAC
error drifts are almost identical.
Logically this means the drift must be in a component which is common to
both ADC and DAC, and which is part of the gain setting circuit.
A look at the schematic and the obvious candidate is the photomos
relays, which are AQY221N3M.
The data sheet for these says the on resistance is typically 5.5R,
however there is a temperature dependency graph, which shows the on
resistance varies from about 4R to 7.5R over the range 0 to 70
degrees.
Given the low impedance of the rest of this part of the circuit, that
drift easily accounts for the measured 1% error drifts, and will
completely dominate any drift in the precision resistors.
Panasonic make a lower resistance version AQY221R2M with resistance
drift from about 0.5R to 1.5R (it is a small graph) over 0 to 70
degrees, but it has much higher capacitance at 14pF (instead of 1.1pF),
which will probably effect the high frequency response.
While this might be worth a simple trial, the loss of high frequency
response may make it unusable, even though I am fairly sure it would
greatly improve the ADC and DAC gain temperature drift.
Best regards
Steve
Please refer to the measurements reports
https://www.ohwr.org/project/fmc-adc-100m14b4cha-hw/wikis/Documents/2017-and-2018-Integration-and-Measurement-resultshttps://ohwr.org/project/fmc-adc-100m14b4cha-hw/issues/2V5 - Improving temperature compensation2019-08-05T09:42:09ZErik van der BijV5 - Improving temperature compensationSundance suggested:
The graphs for both ADC and DAC gains are all close to a straight a
line, so a simple 2 point temperature correction calibration would
reduce these errors by at least an order of magnitude.
Consider the above suggestion for a straight line software gain
correction, instead of the existing single point gain correction. This
requires no hardware changes, and the driver modifications could handle
boards calibrated with either a single or double point gain correction.
Please refer to the measurements reports
https://www.ohwr.org/project/fmc-adc-100m14b4cha-hw/wikis/Documents/2017-and-2018-Integration-and-Measurement-resultsDimitris LampridisDimitris Lampridis