Memory map for spec-fmc-adc-v1.0
BAR0 (1MB):*
| | |* SDB version, offset (bytes) *|Description|Peripherals|Internal mapping|Status| |0x00000|SDB header|SDB specification|-|Available| |0x01000|DMA Controller|DMA config. and status|Registers|Available| |0x01100|Carrier SPI master|DAC control (driving VCXO)|Registers|Not implemented 1| |0x01200|Carrier 1-wire master|Thermometer + unique ID DS18B20|Registers|Available| |0x01300|Carrier CSR|PLL, DDR status, LED control, etc...|Registers|Available| |0x01400|UTC core|Trigger, acq time-tags|Registers|Available| |0x01500|Interrupt controller|Enable mask, irq source|Registers|Available| |0x01600|Mezzanine system management I2C master|0x50) EEPROM (FMC standard) 24AA64T|Registers|Available| |0x01700|Mezzanine SPI master|0) ADC LTC2174, 1->4) DAC (for DC offset) MAX5442|Registers|Available| |0x01800|Mezzanine I2C master|0x55) Oscillator (sampling clock) Si570|Registers|Available| |0x01900|Mezzanine ADC core CSR|ACQ state machine, input range, trigger, etc...|Registers|Available| |0x01A00|Mezzanine 1-wire master|Thermometer + unique ID DS18B20|Registers|Available|
1 Will be used by the White Rabbit (WR) core in a future WR enabled version of the gateware.