-
Matthieu Cattin authored
The sampling frequency can't be changed dynamically in the current design. This is due to the internal fpga pll that is configured for a fixed 400MHz input.
d27e5a09
The sampling frequency can't be changed dynamically in the current design. This is due to the internal fpga pll that is configured for a fixed 400MHz input.
Name |
Last commit
|
Last update |
---|---|---|
.. | ||
Manifest.py | Loading commit data... | |
fmc_adc_100Ms_core.vhd | Loading commit data... | |
fmc_adc_100Ms_core_pkg.vhd | Loading commit data... | |
fmc_adc_100Ms_csr.vhd | Loading commit data... | |
fmc_adc_eic.vhd | Loading commit data... | |
fmc_adc_mezzanine.vhd | Loading commit data... | |
fmc_adc_mezzanine_pkg.vhd | Loading commit data... | |
offset_gain.vhd | Loading commit data... | |
offset_gain_s.vhd | Loading commit data... | |
offset_gain_s_tb.vhd | Loading commit data... | |
offset_gain_tb.vhd | Loading commit data... | |
var_sat_s.vhd | Loading commit data... |