carrier_csr

Carrier control and status registers

Wishbone slave for control and status registers related to the FMC carrier

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Carrier type and PCB version
3.2. Status
3.3. Control
3.4. Reset Register

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Carrier type and PCB version carrier_csr_carrier CARRIER
0x1 REG Status carrier_csr_stat STAT
0x2 REG Control carrier_csr_ctrl CTRL
0x3 REG Reset Register carrier_csr_rst RST

2. HDL symbol

rst_n_i Carrier type and PCB version:
clk_sys_i carrier_csr_carrier_pcb_rev_i[3:0]
wb_adr_i[1:0] carrier_csr_carrier_reserved_i[11:0]
wb_dat_i[31:0] carrier_csr_carrier_type_i[15:0]
wb_dat_o[31:0]  
wb_cyc_i Status:
wb_sel_i[3:0] carrier_csr_stat_fmc_pres_i
wb_stb_i carrier_csr_stat_p2l_pll_lck_i
wb_we_i carrier_csr_stat_sys_pll_lck_i
wb_ack_o carrier_csr_stat_ddr3_cal_done_i
wb_stall_o carrier_csr_stat_reserved_i[27:0]
 
Control:
carrier_csr_ctrl_led_green_o
carrier_csr_ctrl_led_red_o
carrier_csr_ctrl_dac_clr_n_o
carrier_csr_ctrl_reserved_o[28:0]
 
Reset Register:
carrier_csr_rst_fmc0_n_o
carrier_csr_rst_reserved_o[30:0]

3. Register description

3.1. Carrier type and PCB version

HW prefix: carrier_csr_carrier
HW address: 0x0
C prefix: CARRIER
C offset: 0x0
31 30 29 28 27 26 25 24
TYPE[15:8]
23 22 21 20 19 18 17 16
TYPE[7:0]
15 14 13 12 11 10 9 8
RESERVED[11:4]
7 6 5 4 3 2 1 0
RESERVED[3:0] PCB_REV[3:0]

3.2. Status

HW prefix: carrier_csr_stat
HW address: 0x1
C prefix: STAT
C offset: 0x4
31 30 29 28 27 26 25 24
RESERVED[27:20]
23 22 21 20 19 18 17 16
RESERVED[19:12]
15 14 13 12 11 10 9 8
RESERVED[11:4]
7 6 5 4 3 2 1 0
RESERVED[3:0] DDR3_CAL_DONE SYS_PLL_LCK P2L_PLL_LCK FMC_PRES

3.3. Control

HW prefix: carrier_csr_ctrl
HW address: 0x2
C prefix: CTRL
C offset: 0x8
31 30 29 28 27 26 25 24
RESERVED[28:21]
23 22 21 20 19 18 17 16
RESERVED[20:13]
15 14 13 12 11 10 9 8
RESERVED[12:5]
7 6 5 4 3 2 1 0
RESERVED[4:0] DAC_CLR_N LED_RED LED_GREEN

3.4. Reset Register

HW prefix: carrier_csr_rst
HW address: 0x3
C prefix: RST
C offset: 0xc

Controls software reset of the mezzanine including the ddr interface and the time-tagging core.

31 30 29 28 27 26 25 24
RESERVED[30:23]
23 22 21 20 19 18 17 16
RESERVED[22:15]
15 14 13 12 11 10 9 8
RESERVED[14:7]
7 6 5 4 3 2 1 0
RESERVED[6:0] FMC0_N