FMC ADC 100M 14b 4cha - Gateware issueshttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/issues2019-08-05T10:49:09Zhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/issues/38Simulation: add ADC functional model2019-08-05T10:49:09ZDimitris LampridisSimulation: add ADC functional modelIdeally, we should provide an ADC functional model capable of providing
realistic inputs to our module, and ADC core test and verification
class, which we should use then in both the SPEC and SVEC testbenches.
Furthermore, these testbenches should be used to test all features of
the ADC core and provide clear pass/fail return values.https://ohwr.org/project/fmc-adc-100m14b4cha-gw/issues/11Discipline the ADC sampling clock with WR2019-08-05T10:50:32ZDimitris LampridisDiscipline the ADC sampling clock with WRDiscipline the 100MHz sampling clock with WR, in order to have multiple
ADCs with synchonized sampling.https://ohwr.org/project/fmc-adc-100m14b4cha-gw/issues/21Expose more info in the status and/or interrupt registers2019-08-05T11:16:43ZDimitris LampridisExpose more info in the status and/or interrupt registersIn particular various error flags.
Taken from v4.0 gateware manual:
Add error flags to status reg (+interrupt?):
\- Instead of overwriting memory for a given acquisition.
\- If read during acquisition (or even block read during acq?).
Also, add over-heat and input over-load interrupts (from original
specification)V5.0 gateware releaseDimitris LampridisDimitris Lampridishttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/issues/22Cannot use last DPRAM sample2019-08-05T11:16:41ZDimitris LampridisCannot use last DPRAM sampleIf in multi-shot mode an acquisition makes use of the full DPRAM, the
data is delivered to the host corrupt. The cause of this should be
investigated and fixed.
For now (release 4.1), there is a limit in place inside the gateware
which only allows for using "max-1" samples, effectively masking the bug
from the higher layers (driver, apps).V5.0 gateware releaseDimitris LampridisDimitris Lampridishttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/issues/23Account for trigger sample in post-trigger samples2019-08-05T11:16:39ZDimitris LampridisAccount for trigger sample in post-trigger samplesThe "extra" trigger sample is a source of confusion during communication
between gateware, drivers and applications developers.
It makes much more sense to "absorb" the trigger sample into the
post-trigger samples. Thus, a post-samples value of 1 will mean that
only the trigger sample will be acquiredV5.0 gateware releaseDimitris LampridisDimitris Lampridishttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/issues/24Implement trigger hold-off in multi-shot mode2019-08-05T11:39:13ZDimitris LampridisImplement trigger hold-off in multi-shot modeA trigger hold-off (an obligatory "dead time") can be implemented
(probably during the DECR\_SHOT FSM state) in order to limit the trigger
frequency of the FMC-ADC in multi-shot modehttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/issues/27Stream directly to DDR in multi-shot mode2019-08-05T11:39:17ZDimitris LampridisStream directly to DDR in multi-shot modeIn multi-shot mode, the number of samples per trigger is limited by the
size of the on-chip DPRAMs.
Future versions could perhaps completely lift this limitation and stream
directly to the DDR memory (similar to single-shot mode)https://ohwr.org/project/fmc-adc-100m14b4cha-gw/issues/33hdl - Add de-interleave option for data reading2019-08-05T11:39:20ZProjectshdl - Add de-interleave option for data readingIn the DDR memory, data are stored interleaved:
ch1[0], ch2[0], ch3[0], ch4[0], ch1[1], ch2[1], ch3[1], ch4[1]
This is because the DDR memory is used as a circular buffer (data are
written straight to the DDR).
A option should be implemented to read the data in de-interleaved way:
ch1[0], ch1[1], ch2[0], ch2[1], ch3[0], ch3[1], ch4[0], ch4[1]
This should improve the overall readout performance, because without
this option the re-ordering is done in software.