Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This is a manual edit to add 'X' initial values to the register read vector.

This helps a lot with the Xilinx implementation of the code (wrt timing).

This is automatically done by cheby-1.4, but a) it's not released yet and b) when tested,
it created other timing issues.

So for now we stay with cheby-1.3 and manual edit of the vhd files.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This helps with timing, but also provides a more logical structure
for the registers, but not having to manually copy 4 times the same
set of registers (once for each channel).
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Addresses HT-610
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Addresses HT-608, needed by HT-607.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

In order to get latest releases and dma misaligment fix.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

both SPEC and SVEC designs easily meet timing now.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

[hdl] manually drive cheby-generated WB read data to 'X' for non-defined addresses. This helps with meeting timing because of smaller and simpler multiplexer logic.