Commits · master · Projects / FMC ADC 100M 14b 4cha - Gateware

08 Apr, 2016 1 commit
- hdl/sim: sanitized and updated SVEC simulation. Tested with ModelSIM 10.2a, works. · 426788b5
  Dimitris Lampridis authored Apr 08, 2016
  
  426788b5
01 Apr, 2016 1 commit
- hdl/testbench: corrected and expanded new system verilog testbench for SPEC. Tested, works · bfce7558
  Dimitris Lampridis authored Apr 01, 2016
  
  bfce7558
31 Mar, 2016 1 commit
- hdl/sim: sanitized and updated SPEC simulation. Tested with ModelSIM 10.2a,… · 523e8a0a
  Dimitris Lampridis authored Mar 31, 2016
```
hdl/sim: sanitized and updated SPEC simulation. Tested with ModelSIM 10.2a, works. Did not verify simulation results
```
  523e8a0a
20 Aug, 2014 1 commit
- git: define dependencies as git submodules. · 70a2a755
  Matthieu Cattin authored Aug 20, 2014
  
  70a2a755
12 May, 2014 1 commit

Matthieu Cattin authored May 12, 2014

- Rename folders with shorter names.
- Remove documents un-related to gateware (e.g. board design).

94c7ce24

29 Jul, 2013 1 commit
- git: Add .bin and .bit to gitignore file. · e8ce11fd
  Matthieu Cattin authored Jul 29, 2013
  
  e8ce11fd
23 Jul, 2013 1 commit
- git: Update .gitignore file. · b76b7cba
  Matthieu Cattin authored Jul 23, 2013
  
  b76b7cba
19 Jul, 2013 1 commit
- sim, git: Update spec simulation files and gitignore. · 1834a7e3
  Matthieu Cattin authored Jul 19, 2013
  
  1834a7e3
17 Jul, 2013 2 commits
- git: Update gitignore file to add svec files and make it more generic. · 8d188d60
  Matthieu Cattin authored Jul 17, 2013
  
  8d188d60
- hdl: Move ip_cores dir outside of the spec dir. · 00c50f91
  Matthieu Cattin authored Jul 04, 2013
```
The ip_cores dir is meant to be shared between different carriers.
```
  00c50f91
30 Nov, 2012 1 commit
- Add gitignore file. · 1fce251d
  Matthieu Cattin authored Nov 30, 2012
  
  1fce251d