- Rename folders with shorter names.
- Remove documents un-related to gateware (e.g. board design).

- fixed and variable saturation blocks merged into one.
- registers added before the crossbar in the fmc-adc mezzanine component.
- acq_config_ok signal is now registered.

It was creating a big multiplexer in the wishbone crossbar and violating timing constrains.
Those reserved fields are replaced by "don't care" -> better optimised during synthesis.

- Variable data saturation.
- Optional trigger threshold detection deglitch filter.
- Internal trigger test mode.
- Sampling frequency counter.
- Remaining shot counter.
- Defined DAC (for VCXO) control outputs value.
- Check number of samples in multi-shot (shouldn't exceed ram depth).

hdl: Add spexi top hdl design (Note that it's not compliant to the latest architecture and gnum core, yet).

The new GN4124 core version implements a timeout and ERR treatment on the csr wishbone interface.

-> memory map changed!