- Variable data saturation.
- Optional trigger threshold detection deglitch filter.
- Internal trigger test mode.
- Sampling frequency counter.
- Remaining shot counter.
- Defined DAC (for VCXO) control outputs value.
- Check number of samples in multi-shot (shouldn't exceed ram depth).

hdl: Add spexi top hdl design (Note that it's not compliant to the latest architecture and gnum core, yet).

The new GN4124 core version implements a timeout and ERR treatment on the csr wishbone interface.

-> memory map changed!

hdl: Fix ddr adr and data wb slave number, add carrier type generic, increment ddr address counter on cyc falling edge.