Commits · 05b0eeedc470776b9dfb94e4a2e798e8ff9d73b6 · Projects / FMC ADC 100M 14b 4cha

30 Aug, 2012 1 commit

Update fmc_adc_100Ms_csr documentation. · 05b0eeed

mcattin authored Aug 30, 2012


git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@129 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

05b0eeed

29 Aug, 2012 1 commit

Add user guide Latex source and Makefile. · a7180ffc

mcattin authored Aug 29, 2012

Move drawings to figures folder.



git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@128 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

a7180ffc

16 Aug, 2012 1 commit

Update fmc_adc_100Ms_csr documentation. · 64798771

mcattin authored Aug 16, 2012

Add more details on data format.



git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@127 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

64798771

06 Aug, 2012 1 commit

Update general-cores library components interfaces. · 91a35cb4

mcattin authored Aug 06, 2012

Wishbone components map updated to fit the new entities.
 -> generic to select interface mode (classic/pipelined) and address granularity (byte/word).
 -> wishbone address port size.



git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@126 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

91a35cb4

11 Jul, 2012 2 commits

Update DDR core. · d63286ab

mcattin authored Jul 11, 2012

New generated core naming.


git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@125 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

d63286ab

Updated DDR core. · e46239ae

mcattin authored Jul 11, 2012

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@124 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

e46239ae

09 Jul, 2012 1 commit

Change end of acquisition interrupt generation. · 468ef662

mcattin authored Jul 09, 2012

Now the interrupt is generated when the DDR interface write FIFO is empty.
This is to avoid read request from the host before all data are written to the DDR memory.

Add synthesis, p&r and timing reports.
Remove generated simulation files from repo.

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@123 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

468ef662

05 Jul, 2012 2 commits

Modify sim Manifest to take monostable and ext_pulse_sync from ip_cores directory. · 990cc919
mcattin authored Jul 05, 2012
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@122 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
990cc919

Fix bug in trigger delay. · ace6eb31

mcattin authored Jul 05, 2012

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@121 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

ace6eb31

04 May, 2012 1 commit
- Update ADC core registers description. Add details on SSR usage in channels control register. · a397aecb
  mcattin authored May 04, 2012
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@120 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
  a397aecb
06 Feb, 2012 2 commits

Add LGPL header. · dc01a1c9

mcattin authored Feb 06, 2012

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@118 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

dc01a1c9

Add LGPL license to hdl top folder. · a0ed4002

mcattin authored Feb 06, 2012

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@117 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

a0ed4002

26 Jan, 2012 1 commit

Change internal hw trigger to two's complement comparison. Update threshold… · 0d587a34

mcattin authored Jan 26, 2012

Change internal hw trigger to two's complement comparison. Update threshold register comment for wbgen.

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@114 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

0d587a34

18 Jan, 2012 2 commits

Change path to wbgen2 in Makefiles. · 492231fe

mcattin authored Jan 18, 2012

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@113 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

492231fe

Add bit description for IRQ controller registers. · af2eaddf

mcattin authored Jan 18, 2012

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@112 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

af2eaddf

06 Jan, 2012 1 commit

Add simulation folder to repo. · 78c670fe

mcattin authored Jan 06, 2012

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@110 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

78c670fe

16 Dec, 2011 1 commit
- Change offset gain correction block to signed, data from ADC is two's complement. · cbc4c992
  mcattin authored Dec 16, 2011
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@104 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
  cbc4c992
15 Dec, 2011 1 commit
- Add signed version of offset gain module, to be used with tow's complement data from ADC. · a7afca0e
  mcattin authored Dec 15, 2011
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@103 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
  a7afca0e
02 Dec, 2011 1 commit

Add block diagram of architecture and ADC core. · 3642c1a7

mcattin authored Dec 02, 2011

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@101 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

3642c1a7

01 Dec, 2011 1 commit
- Fix bug in multi-shot, last shot was read from the wrong buffer. · 85e88415
  mcattin authored Dec 01, 2011
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@100 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
  85e88415
28 Nov, 2011 1 commit
- Fix number of samples written to DDR in multi-shot. There was 1 extra pre-trigger sample. · d9adaa4e
  mcattin authored Nov 28, 2011
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@99 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
  d9adaa4e
25 Nov, 2011 2 commits

Add offset_gain entity. · 62f5c1ec

mcattin authored Nov 25, 2011

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@98 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

62f5c1ec

Add gain/offset calibration, fix pre/post trigger sample number. · 0fb16384
mcattin authored Nov 25, 2011
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@97 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
0fb16384

23 Nov, 2011 5 commits
- Replace unused bits in registers by reserved. · 39353cd0
  mcattin authored Nov 23, 2011
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@96 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
  39353cd0
- Add Trigger address register. Filter out trigger pulses outside of WAIT_TRIG state. · c2285a38
  mcattin authored Nov 23, 2011
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@95 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
  c2285a38
- Add a bit to the FIFO to pass the trigger as well. Reduce FIFO depth to 64 (was 1024). · 89ee4559
  mcattin authored Nov 23, 2011
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@94 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
  89ee4559
- Replace empty bits in registers by reserved. · cdfee3dd
  mcattin authored Nov 23, 2011
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@93 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
  cdfee3dd
- Remove utc registers. Add trigger address, gain and offset calibration registers. · e7e2f3c9
  mcattin authored Nov 23, 2011
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@92 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
  e7e2f3c9
22 Nov, 2011 4 commits
- Fix bug in multi-shot mode. wb_fifo wr_en signal was badly assigned. · 9f574761
  mcattin authored Nov 22, 2011
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@91 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
  9f574761
- Fix utc_core addr width and utc coarse counter overflow limit. · 13cce547
  mcattin authored Nov 22, 2011
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@90 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
  13cce547
- Add acq_end output to adc_core for irq and time-tag. · 12621ca0
  mcattin authored Nov 22, 2011
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@89 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
  12621ca0
- One multiple irq bit per irq source instead of a unique flag. · e948330f
  mcattin authored Nov 22, 2011
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@88 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
  e948330f
18 Nov, 2011 3 commits

Fix typo in register name. · 413ce60d

mcattin authored Nov 18, 2011

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@87 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

413ce60d

Add UTC core, IRQ controller and 1-wire for carrier ID/temp to design. · 235c95da
mcattin authored Nov 18, 2011
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@86 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
235c95da

Add UTC core and IRQ controller to repo. · 0e9e8084

mcattin authored Nov 18, 2011

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@85 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

0e9e8084

17 Nov, 2011 2 commits

Update chipscope project. · 0840bffd

mcattin authored Nov 17, 2011

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@84 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

0840bffd

Add utc core registers generated with wbgen2. · 1233efd9

mcattin authored Nov 17, 2011

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@83 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

1233efd9

16 Nov, 2011 3 commits
- Add a BUFG on the adc serdes PLL feedback path, add termination on LVDS data line from ADC. · f513a2b9
  mcattin authored Nov 16, 2011
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@82 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
  f513a2b9
- Commit some chipscope projects. · 1fb0e23d
  mcattin authored Nov 16, 2011
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@81 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
  1fb0e23d
- Add monostable, ext_pulse_sync and utils_pkg to repo. Where only localy on my pc. · 35758780
  mcattin authored Nov 16, 2011
```
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@80 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
```
  35758780