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FMC ADC 100M 14b 4cha - Gateware
Commit f9628bce authored by Matthieu Cattin's avatar Matthieu Cattin
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hdl: Increase decimation register width from 16 to 32 bits.

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documentation/manuals/firmware/fmc_adc_100Ms_csr.tex
View file @ f9628bce
...@@ -300,21 +300,15 @@ Trigger address ...@@ -300,21 +300,15 @@ Trigger address
@regsection @code{sr} - Sample rate @regsection @code{sr} - Sample rate
@multitable @columnfractions .10 .10 .15 .10 .55 @multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name @headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0} @item @code{31...0}
@tab R/W @tab @tab R/W @tab
@code{DECI} @code{DECI}
@tab @code{0} @tab @tab @code{0} @tab
Sample rate decimation Sample rate decimation
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable @end multitable
@multitable @columnfractions 0.15 0.85 @multitable @columnfractions 0.15 0.85
@headitem Field @tab Description @headitem Field @tab Description
@item @code{deci} @tab Decimation factor. Takes one sample every N samples and discards the others (N = decimation factor). @item @code{deci} @tab Decimation factor. Takes one sample every N samples and discards the others (N = decimation factor).
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable @end multitable
@regsection @code{pre_samples} - Pre-trigger samples @regsection @code{pre_samples} - Pre-trigger samples
@multitable @columnfractions .10 .10 .15 .10 .55 @multitable @columnfractions .10 .10 .15 .10 .55
......
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ f9628bce
...@@ -182,8 +182,7 @@ architecture rtl of fmc_adc_100Ms_core is ...@@ -182,8 +182,7 @@ architecture rtl of fmc_adc_100Ms_core is
fmc_adc_core_shots_nb_o : out std_logic_vector(15 downto 0); fmc_adc_core_shots_nb_o : out std_logic_vector(15 downto 0);
fmc_adc_core_shots_reserved_o : out std_logic_vector(15 downto 0); fmc_adc_core_shots_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_trig_pos_i : in std_logic_vector(31 downto 0); fmc_adc_core_trig_pos_i : in std_logic_vector(31 downto 0);
fmc_adc_core_sr_deci_o : out std_logic_vector(15 downto 0); fmc_adc_core_sr_deci_o : out std_logic_vector(31 downto 0);
fmc_adc_core_sr_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_pre_samples_o : out std_logic_vector(31 downto 0); fmc_adc_core_pre_samples_o : out std_logic_vector(31 downto 0);
fmc_adc_core_post_samples_o : out std_logic_vector(31 downto 0); fmc_adc_core_post_samples_o : out std_logic_vector(31 downto 0);
fmc_adc_core_samples_cnt_i : in std_logic_vector(31 downto 0); fmc_adc_core_samples_cnt_i : in std_logic_vector(31 downto 0);
...@@ -335,8 +334,8 @@ architecture rtl of fmc_adc_100Ms_core is ...@@ -335,8 +334,8 @@ architecture rtl of fmc_adc_100Ms_core is
signal trig_align : std_logic; signal trig_align : std_logic;
-- Decimation -- Decimation
signal decim_factor : std_logic_vector(15 downto 0); signal decim_factor : std_logic_vector(31 downto 0);
signal decim_cnt : unsigned(15 downto 0); signal decim_cnt : unsigned(31 downto 0);
signal decim_en : std_logic; signal decim_en : std_logic;
-- Sync FIFO (from fs_clk to sys_clk_i) -- Sync FIFO (from fs_clk to sys_clk_i)
...@@ -713,7 +712,6 @@ begin ...@@ -713,7 +712,6 @@ begin
fmc_adc_core_shots_reserved_o => open, fmc_adc_core_shots_reserved_o => open,
fmc_adc_core_trig_pos_i => trig_addr, fmc_adc_core_trig_pos_i => trig_addr,
fmc_adc_core_sr_deci_o => decim_factor, fmc_adc_core_sr_deci_o => decim_factor,
fmc_adc_core_sr_reserved_o => open,
fmc_adc_core_pre_samples_o => pre_trig_value, fmc_adc_core_pre_samples_o => pre_trig_value,
fmc_adc_core_post_samples_o => post_trig_value, fmc_adc_core_post_samples_o => post_trig_value,
fmc_adc_core_samples_cnt_i => std_logic_vector(samples_cnt), fmc_adc_core_samples_cnt_i => std_logic_vector(samples_cnt),
...@@ -885,7 +883,7 @@ begin ...@@ -885,7 +883,7 @@ begin
decim_en <= '0'; decim_en <= '0';
elsif rising_edge(fs_clk) then elsif rising_edge(fs_clk) then
if decim_cnt = to_unsigned(0, decim_cnt'length) then if decim_cnt = to_unsigned(0, decim_cnt'length) then
if decim_factor /= X"0000" then if decim_factor /= X"00000000" then
decim_cnt <= unsigned(decim_factor) - 1; decim_cnt <= unsigned(decim_factor) - 1;
end if; end if;
decim_en <= '1'; decim_en <= '1';
......
hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
View file @ f9628bce
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd -- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb -- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Tue Jul 23 14:30:38 2013 -- Created : Wed Aug 7 17:44:15 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
...@@ -79,9 +79,7 @@ entity fmc_adc_100Ms_csr is ...@@ -79,9 +79,7 @@ entity fmc_adc_100Ms_csr is
-- Port for std_logic_vector field: 'Trigger address' in reg: 'Trigger address register' -- Port for std_logic_vector field: 'Trigger address' in reg: 'Trigger address register'
fmc_adc_core_trig_pos_i : in std_logic_vector(31 downto 0); fmc_adc_core_trig_pos_i : in std_logic_vector(31 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Sample rate decimation' in reg: 'Sample rate' -- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Sample rate decimation' in reg: 'Sample rate'
fmc_adc_core_sr_deci_o : out std_logic_vector(15 downto 0); fmc_adc_core_sr_deci_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Sample rate'
fmc_adc_core_sr_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Pre-trigger samples' in reg: 'Pre-trigger samples' -- Port for std_logic_vector field: 'Pre-trigger samples' in reg: 'Pre-trigger samples'
fmc_adc_core_pre_samples_o : out std_logic_vector(31 downto 0); fmc_adc_core_pre_samples_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Post-trigger samples' in reg: 'Post-trigger samples' -- Port for std_logic_vector field: 'Post-trigger samples' in reg: 'Post-trigger samples'
...@@ -201,13 +199,12 @@ signal fmc_adc_core_sw_trig_wr_sync1 : std_logic ; ...@@ -201,13 +199,12 @@ signal fmc_adc_core_sw_trig_wr_sync1 : std_logic ;
signal fmc_adc_core_sw_trig_wr_sync2 : std_logic ; signal fmc_adc_core_sw_trig_wr_sync2 : std_logic ;
signal fmc_adc_core_shots_nb_int : std_logic_vector(15 downto 0); signal fmc_adc_core_shots_nb_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_shots_reserved_int : std_logic_vector(15 downto 0); signal fmc_adc_core_shots_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_sr_deci_int : std_logic_vector(15 downto 0); signal fmc_adc_core_sr_deci_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_sr_deci_swb : std_logic ; signal fmc_adc_core_sr_deci_swb : std_logic ;
signal fmc_adc_core_sr_deci_swb_delay : std_logic ; signal fmc_adc_core_sr_deci_swb_delay : std_logic ;
signal fmc_adc_core_sr_deci_swb_s0 : std_logic ; signal fmc_adc_core_sr_deci_swb_s0 : std_logic ;
signal fmc_adc_core_sr_deci_swb_s1 : std_logic ; signal fmc_adc_core_sr_deci_swb_s1 : std_logic ;
signal fmc_adc_core_sr_deci_swb_s2 : std_logic ; signal fmc_adc_core_sr_deci_swb_s2 : std_logic ;
signal fmc_adc_core_sr_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_pre_samples_int : std_logic_vector(31 downto 0); signal fmc_adc_core_pre_samples_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_post_samples_int : std_logic_vector(31 downto 0); signal fmc_adc_core_post_samples_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_ch1_ctl_ssr_int : std_logic_vector(6 downto 0); signal fmc_adc_core_ch1_ctl_ssr_int : std_logic_vector(6 downto 0);
...@@ -314,10 +311,9 @@ begin ...@@ -314,10 +311,9 @@ begin
fmc_adc_core_sw_trig_wr_int_delay <= '0'; fmc_adc_core_sw_trig_wr_int_delay <= '0';
fmc_adc_core_shots_nb_int <= "0000000000000000"; fmc_adc_core_shots_nb_int <= "0000000000000000";
fmc_adc_core_shots_reserved_int <= "0000000000000000"; fmc_adc_core_shots_reserved_int <= "0000000000000000";
fmc_adc_core_sr_deci_int <= "0000000000000000"; fmc_adc_core_sr_deci_int <= "00000000000000000000000000000000";
fmc_adc_core_sr_deci_swb <= '0'; fmc_adc_core_sr_deci_swb <= '0';
fmc_adc_core_sr_deci_swb_delay <= '0'; fmc_adc_core_sr_deci_swb_delay <= '0';
fmc_adc_core_sr_reserved_int <= "0000000000000000";
fmc_adc_core_pre_samples_int <= "00000000000000000000000000000000"; fmc_adc_core_pre_samples_int <= "00000000000000000000000000000000";
fmc_adc_core_post_samples_int <= "00000000000000000000000000000000"; fmc_adc_core_post_samples_int <= "00000000000000000000000000000000";
fmc_adc_core_ch1_ctl_ssr_int <= "0000000"; fmc_adc_core_ch1_ctl_ssr_int <= "0000000";
...@@ -522,13 +518,11 @@ begin ...@@ -522,13 +518,11 @@ begin
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00111" => when "00111" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
fmc_adc_core_sr_deci_int <= wrdata_reg(15 downto 0); fmc_adc_core_sr_deci_int <= wrdata_reg(31 downto 0);
fmc_adc_core_sr_deci_swb <= '1'; fmc_adc_core_sr_deci_swb <= '1';
fmc_adc_core_sr_deci_swb_delay <= '1'; fmc_adc_core_sr_deci_swb_delay <= '1';
fmc_adc_core_sr_reserved_int <= wrdata_reg(31 downto 16);
end if; end if;
rddata_reg(15 downto 0) <= fmc_adc_core_sr_deci_int; rddata_reg(31 downto 0) <= fmc_adc_core_sr_deci_int;
rddata_reg(31 downto 16) <= fmc_adc_core_sr_reserved_int;
ack_sreg(3) <= '1'; ack_sreg(3) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01000" => when "01000" =>
...@@ -891,7 +885,7 @@ begin ...@@ -891,7 +885,7 @@ begin
fmc_adc_core_sr_deci_swb_s0 <= '0'; fmc_adc_core_sr_deci_swb_s0 <= '0';
fmc_adc_core_sr_deci_swb_s1 <= '0'; fmc_adc_core_sr_deci_swb_s1 <= '0';
fmc_adc_core_sr_deci_swb_s2 <= '0'; fmc_adc_core_sr_deci_swb_s2 <= '0';
fmc_adc_core_sr_deci_o <= "0000000000000000"; fmc_adc_core_sr_deci_o <= "00000000000000000000000000000000";
elsif rising_edge(fs_clk_i) then elsif rising_edge(fs_clk_i) then
fmc_adc_core_sr_deci_swb_s0 <= fmc_adc_core_sr_deci_swb; fmc_adc_core_sr_deci_swb_s0 <= fmc_adc_core_sr_deci_swb;
fmc_adc_core_sr_deci_swb_s1 <= fmc_adc_core_sr_deci_swb_s0; fmc_adc_core_sr_deci_swb_s1 <= fmc_adc_core_sr_deci_swb_s0;
...@@ -903,8 +897,6 @@ begin ...@@ -903,8 +897,6 @@ begin
end process; end process;
-- Reserved
fmc_adc_core_sr_reserved_o <= fmc_adc_core_sr_reserved_int;
-- Pre-trigger samples -- Pre-trigger samples
fmc_adc_core_pre_samples_o <= fmc_adc_core_pre_samples_int; fmc_adc_core_pre_samples_o <= fmc_adc_core_pre_samples_int;
-- Post-trigger samples -- Post-trigger samples
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
View file @ f9628bce
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h * File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb * Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Tue Jul 23 14:30:38 2013 * Created : Wed Aug 7 17:44:15 2013
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
...@@ -138,16 +138,10 @@ ...@@ -138,16 +138,10 @@
/* definitions for register: Sample rate */ /* definitions for register: Sample rate */
/* definitions for field: Sample rate decimation in reg: Sample rate */ /* definitions for field: Sample rate decimation in reg: Sample rate */
#define FMC_ADC_CORE_SR_DECI_MASK WBGEN2_GEN_MASK(0, 16) #define FMC_ADC_CORE_SR_DECI_MASK WBGEN2_GEN_MASK(0, 32)
#define FMC_ADC_CORE_SR_DECI_SHIFT 0 #define FMC_ADC_CORE_SR_DECI_SHIFT 0
#define FMC_ADC_CORE_SR_DECI_W(value) WBGEN2_GEN_WRITE(value, 0, 16) #define FMC_ADC_CORE_SR_DECI_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define FMC_ADC_CORE_SR_DECI_R(reg) WBGEN2_GEN_READ(reg, 0, 16) #define FMC_ADC_CORE_SR_DECI_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for field: Reserved in reg: Sample rate */
#define FMC_ADC_CORE_SR_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_SR_RESERVED_SHIFT 16
#define FMC_ADC_CORE_SR_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_SR_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Pre-trigger samples */ /* definitions for register: Pre-trigger samples */
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
View file @ f9628bce
...@@ -1251,24 +1251,7 @@ fmc_adc_core_trig_pos_i[31:0] ...@@ -1251,24 +1251,7 @@ fmc_adc_core_trig_pos_i[31:0]
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
fmc_adc_core_sr_deci_o[15:0] fmc_adc_core_sr_deci_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_sr_reserved_o[15:0]
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
&rArr; &rArr;
...@@ -4456,7 +4439,7 @@ SR ...@@ -4456,7 +4439,7 @@ SR
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8] DECI[31:24]
</td> </td>
<td > <td >
...@@ -4510,7 +4493,7 @@ RESERVED[15:8] ...@@ -4510,7 +4493,7 @@ RESERVED[15:8]
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0] DECI[23:16]
</td> </td>
<td > <td >
...@@ -4648,10 +4631,6 @@ DECI[7:0] ...@@ -4648,10 +4631,6 @@ DECI[7:0]
DECI DECI
</b>[<i>read/write</i>]: Sample rate decimation </b>[<i>read/write</i>]: Sample rate decimation
<br>Decimation factor. Takes one sample every N samples and discards the others (N = decimation factor). <br>Decimation factor. Takes one sample every N samples and discards the others (N = decimation factor).
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul> </ul>
<a name="PRE_SAMPLES"></a> <a name="PRE_SAMPLES"></a>
<h3><a name="sect_3_9">3.9. Pre-trigger samples</a></h3> <h3><a name="sect_3_9">3.9. Pre-trigger samples</a></h3>
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
View file @ f9628bce
...@@ -275,21 +275,11 @@ peripheral { ...@@ -275,21 +275,11 @@ peripheral {
description = "Decimation factor. Takes one sample every N samples and discards the others (N = decimation factor)."; description = "Decimation factor. Takes one sample every N samples and discards the others (N = decimation factor).";
prefix = "deci"; prefix = "deci";
type = SLV; type = SLV;
size = 16; size = 32;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
clock = "fs_clk_i"; clock = "fs_clk_i";
}; };
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
}; };
reg { reg {
......
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