Commit f61a80f5 authored by Matthieu Cattin's avatar Matthieu Cattin

hdl: Update wbgen2 and re-generate cores.

parent 5f189f2c
......@@ -82,22 +82,22 @@ Reserved
@item @code{0}
@tab R/W @tab
@code{LED_GREEN}
@tab @code{X} @tab
@tab @code{0} @tab
Green LED
@item @code{1}
@tab R/W @tab
@code{LED_RED}
@tab @code{X} @tab
@tab @code{0} @tab
Red LED
@item @code{2}
@tab R/W @tab
@code{DAC_CLR_N}
@tab @code{X} @tab
@tab @code{0} @tab
DAC clear
@item @code{31...3}
@tab R/W @tab
@code{RESERVED}
@tab @code{X} @tab
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
......
......@@ -116,42 +116,42 @@ Channel 4 offset calibration register
@item @code{1...0}
@tab R/W @tab
@code{FSM_CMD}
@tab @code{X} @tab
@tab @code{0} @tab
State machine commands (ignore on read)
@item @code{2}
@tab R/W @tab
@code{FMC_CLK_OE}
@tab @code{X} @tab
@tab @code{0} @tab
FMC Si750 output enable
@item @code{3}
@tab R/W @tab
@code{OFFSET_DAC_CLR_N}
@tab @code{X} @tab
@tab @code{0} @tab
Offset DACs clear (active low)
@item @code{4}
@tab W/O @tab
@code{MAN_BITSLIP}
@tab @code{X} @tab
@tab @code{0} @tab
Manual serdes bitslip (ignore on read)
@item @code{5}
@tab R/W @tab
@code{TEST_DATA_EN}
@tab @code{X} @tab
@tab @code{0} @tab
Enable test data
@item @code{6}
@tab R/W @tab
@code{TRIG_LED}
@tab @code{X} @tab
@tab @code{0} @tab
Manual TRIG LED
@item @code{7}
@tab R/W @tab
@code{ACQ_LED}
@tab @code{X} @tab
@tab @code{0} @tab
Manual ACQ LED
@item @code{31...8}
@tab R/W @tab
@code{RESERVED}
@tab @code{X} @tab
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -199,37 +199,37 @@ Reserved
@item @code{0}
@tab R/W @tab
@code{HW_TRIG_SEL}
@tab @code{X} @tab
@tab @code{0} @tab
Hardware trigger selection
@item @code{1}
@tab R/W @tab
@code{HW_TRIG_POL}
@tab @code{X} @tab
@tab @code{0} @tab
Hardware trigger polarity
@item @code{2}
@tab R/W @tab
@code{HW_TRIG_EN}
@tab @code{X} @tab
@tab @code{0} @tab
Hardware trigger enable
@item @code{3}
@tab R/W @tab
@code{SW_TRIG_EN}
@tab @code{X} @tab
@tab @code{0} @tab
Software trigger enable
@item @code{5...4}
@tab R/W @tab
@code{INT_TRIG_SEL}
@tab @code{X} @tab
@tab @code{0} @tab
Channel selection for internal trigger
@item @code{15...6}
@tab R/W @tab
@code{RESERVED}
@tab @code{X} @tab
@tab @code{0} @tab
Reserved
@item @code{31...16}
@tab R/W @tab
@code{INT_TRIG_THRES}
@tab @code{X} @tab
@tab @code{0} @tab
Threshold for internal trigger
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -248,7 +248,7 @@ Threshold for internal trigger
@item @code{31...0}
@tab R/W @tab
@code{TRIG_DLY}
@tab @code{X} @tab
@tab @code{0} @tab
Trigger delay value
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -262,24 +262,21 @@ Writing (anything) to this register generates a software trigger.
@item @code{31...0}
@tab W/O @tab
@code{SW_TRIG}
@tab @code{X} @tab
@tab @code{0} @tab
Software trigger (ignore on read)
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code{shots} - Number of shots
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{NB}
@tab @code{X} @tab
@tab @code{0} @tab
Number of shots
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{X} @tab
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -306,12 +303,12 @@ Trigger address
@item @code{15...0}
@tab R/W @tab
@code{DECI}
@tab @code{X} @tab
@tab @code{0} @tab
Sample rate decimation
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{X} @tab
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -325,7 +322,7 @@ Reserved
@item @code{31...0}
@tab R/W @tab
@code{PRE_SAMPLES}
@tab @code{X} @tab
@tab @code{0} @tab
Pre-trigger samples
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -338,7 +335,7 @@ Pre-trigger samples
@item @code{31...0}
@tab R/W @tab
@code{POST_SAMPLES}
@tab @code{X} @tab
@tab @code{0} @tab
Post-trigger samples
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -364,12 +361,12 @@ Samples counter
@item @code{6...0}
@tab R/W @tab
@code{SSR}
@tab @code{X} @tab
@tab @code{0} @tab
Solid state relays control for channel 1
@item @code{31...7}
@tab R/W @tab
@code{RESERVED}
@tab @code{X} @tab
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -402,12 +399,12 @@ Reserved
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{X} @tab
@tab @code{0} @tab
Gain calibration for channel 1
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{X} @tab
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -421,12 +418,12 @@ Reserved
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{X} @tab
@tab @code{0} @tab
Offset calibration for channel 1
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{X} @tab
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -440,12 +437,12 @@ Reserved
@item @code{6...0}
@tab R/W @tab
@code{SSR}
@tab @code{X} @tab
@tab @code{0} @tab
Solid state relays control for channel 2
@item @code{31...7}
@tab R/W @tab
@code{RESERVED}
@tab @code{X} @tab
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -478,12 +475,12 @@ Reserved
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{X} @tab
@tab @code{0} @tab
Gain calibration for channel 2
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{X} @tab
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -497,12 +494,12 @@ Reserved
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{X} @tab
@tab @code{0} @tab
Offset calibration for channel 2
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{X} @tab
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -516,12 +513,12 @@ Reserved
@item @code{6...0}
@tab R/W @tab
@code{SSR}
@tab @code{X} @tab
@tab @code{0} @tab
Solid state relays control for channel 3
@item @code{31...7}
@tab R/W @tab
@code{RESERVED}
@tab @code{X} @tab
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -554,12 +551,12 @@ Reserved
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{X} @tab
@tab @code{0} @tab
Gain calibration for channel 3
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{X} @tab
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -573,12 +570,12 @@ Reserved
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{X} @tab
@tab @code{0} @tab
Offset calibration for channel 3
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{X} @tab
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -592,12 +589,12 @@ Reserved
@item @code{6...0}
@tab R/W @tab
@code{SSR}
@tab @code{X} @tab
@tab @code{0} @tab
Solid state relays control for channel 4
@item @code{31...7}
@tab R/W @tab
@code{RESERVED}
@tab @code{X} @tab
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -630,12 +627,12 @@ Reserved
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{X} @tab
@tab @code{0} @tab
Gain calibration for channel 4
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{X} @tab
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
......@@ -649,12 +646,12 @@ Reserved
@item @code{15...0}
@tab R/W @tab
@code{VAL}
@tab @code{X} @tab
@tab @code{0} @tab
Offset calibration for channel 4
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{X} @tab
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
......
......@@ -15,13 +15,7 @@ REG @tab
Interrupt enable mask register
@end multitable
@regsection @code{multi_irq} - Multiple interrupt register
Multiple interrupts occurs before irq source is read.
Write '1' to clear a bit.
Bit 0: DMA done.
Bit 1: DMA error.
Bit 2: Trigger.
Bit 3: Acquisition end.
Multiple interrupts occurs before irq source is read.@*Write '1' to clear a bit.@*@*Bit 0: DMA done.@*Bit 1: DMA error.@*Bit 2: Trigger.@*Bit 3: Acquisition end.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
......@@ -30,17 +24,8 @@ Bit 3: Acquisition end.
@tab @code{X} @tab
Multiple interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code{src} - Interrupt sources register
Indicates the interrupt source.
Write '1' to clear a bit.
Bit 0: DMA done.
Bit 1: DMA error.
Bit 2: Trigger.
Bit 3: Acquisition end.
Indicates the interrupt source.@*Write '1' to clear a bit.@*@*Bit 0: DMA done.@*Bit 1: DMA error.@*Bit 2: Trigger.@*Bit 3: Acquisition end.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
......@@ -49,24 +34,13 @@ Bit 3: Acquisition end.
@tab @code{X} @tab
Interrupt sources
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code{en_mask} - Interrupt enable mask register
Bit mask to independently enable interrupt sources.
Bit 0: DMA done.
Bit 1: DMA error.
Bit 2: Trigger.
Bit 3: Acquisition end.
Bit mask to independently enable interrupt sources.@*@*Bit 0: DMA done.@*Bit 1: DMA error.@*Bit 2: Trigger.@*Bit 3: Acquisition end.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{EN_MASK}
@tab @code{X} @tab
@tab @code{0} @tab
Interrupt enable mask
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Fri May 3 10:49:18 2013
-- Created : Tue Jul 23 14:30:38 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......
......@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Fri May 3 10:49:18 2013
* Created : Tue Jul 23 14:30:38 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Tue May 7 14:56:42 2013
-- Created : Tue Jul 23 14:34:24 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/irq_controller_regs.vhd
-- Author : auto-generated by wbgen2 from irq_controller_regs.wb
-- Created : Tue May 7 14:57:57 2013
-- Created : Tue Jul 23 14:34:24 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb
......
......@@ -3,7 +3,7 @@
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Tue May 7 14:56:42 2013
* Created : Tue Jul 23 14:34:24 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......
......@@ -3,7 +3,7 @@
* File : irq_controller_regs.h
* Author : auto-generated by wbgen2 from irq_controller_regs.wb
* Created : Tue May 7 14:57:57 2013
* Created : Tue Jul 23 14:34:24 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb
......
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