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FMC ADC 100M 14b 4cha - Gateware
Commit ed969828 authored by mcattin's avatar mcattin
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add manual control for front panel LEDs, change ext trigger min pulse width. 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@73 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent bced5daf
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Showing with 193 additions and 56 deletions
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ ed969828
...@@ -71,14 +71,14 @@ entity fmc_adc_100Ms_core is ...@@ -71,14 +71,14 @@ entity fmc_adc_100Ms_core is
adc_outb_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (even bits) adc_outb_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (even bits)
adc_outb_n_i : in std_logic_vector(3 downto 0); adc_outb_n_i : in std_logic_vector(3 downto 0);
gpio_dac_clr_n_o : out std_logic; -- offset DACs clear (active low) gpio_dac_clr_n_o : out std_logic; -- offset DACs clear (active low)
gpio_led_power_o : out std_logic; -- Mezzanine front panel power LED (PWR) gpio_led_acq_o : out std_logic; -- Mezzanine front panel power LED (PWR)
gpio_led_trigger_o : out std_logic; -- Mezzanine front panel trigger LED (TRIG) gpio_led_trig_o : out std_logic; -- Mezzanine front panel trigger LED (TRIG)
gpio_ssr_ch1_o : out std_logic_vector(6 downto 0); -- Channel 1 solid state relays control gpio_ssr_ch1_o : out std_logic_vector(6 downto 0); -- Channel 1 solid state relays control
gpio_ssr_ch2_o : out std_logic_vector(6 downto 0); -- Channel 2 solid state relays control gpio_ssr_ch2_o : out std_logic_vector(6 downto 0); -- Channel 2 solid state relays control
gpio_ssr_ch3_o : out std_logic_vector(6 downto 0); -- Channel 3 solid state relays control gpio_ssr_ch3_o : out std_logic_vector(6 downto 0); -- Channel 3 solid state relays control
gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control
gpio_si570_oe_o : out std_logic -- Si570 (programmable oscillator) output enable gpio_si570_oe_o : out std_logic -- Si570 (programmable oscillator) output enable
); );
end fmc_adc_100Ms_core; end fmc_adc_100Ms_core;
...@@ -133,6 +133,8 @@ architecture rtl of fmc_adc_100Ms_core is ...@@ -133,6 +133,8 @@ architecture rtl of fmc_adc_100Ms_core is
fmc_adc_core_ctl_offset_dac_clr_n_o : out std_logic; fmc_adc_core_ctl_offset_dac_clr_n_o : out std_logic;
fmc_adc_core_ctl_man_bitslip_o : out std_logic; fmc_adc_core_ctl_man_bitslip_o : out std_logic;
fmc_adc_core_ctl_test_data_en_o : out std_logic; fmc_adc_core_ctl_test_data_en_o : out std_logic;
fmc_adc_core_ctl_trig_led_o : out std_logic;
fmc_adc_core_ctl_acq_led_o : out std_logic;
fmc_adc_core_sta_fsm_i : in std_logic_vector(2 downto 0); fmc_adc_core_sta_fsm_i : in std_logic_vector(2 downto 0);
fmc_adc_core_sta_serdes_pll_i : in std_logic; fmc_adc_core_sta_serdes_pll_i : in std_logic;
fmc_adc_core_sta_serdes_synced_i : in std_logic; fmc_adc_core_sta_serdes_synced_i : in std_logic;
...@@ -385,13 +387,18 @@ architecture rtl of fmc_adc_100Ms_core is ...@@ -385,13 +387,18 @@ architecture rtl of fmc_adc_100Ms_core is
-- Wishbone interface to DDR -- Wishbone interface to DDR
signal wb_ddr_stall_t : std_logic; signal wb_ddr_stall_t : std_logic;
-- LEDs
signal trig_led : std_logic;
signal trig_led_man : std_logic;
signal acq_led_man : std_logic;
begin begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- LEDs -- LEDs
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
gpio_led_power_o <= serdes_synced; gpio_led_acq_o <= samples_wr_en or acq_led_man;
cmp_trig_led_monostable : monostable cmp_trig_led_monostable : monostable
generic map( generic map(
...@@ -404,9 +411,11 @@ begin ...@@ -404,9 +411,11 @@ begin
rst_n_i => sys_rst_n_i, rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i, clk_i => sys_clk_i,
trigger_i => acq_trig, trigger_i => acq_trig,
pulse_o => gpio_led_trigger_o pulse_o => trig_led
); );
gpio_led_trig_o <= trig_led or trig_led_man;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Resets -- Resets
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -583,6 +592,8 @@ begin ...@@ -583,6 +592,8 @@ begin
fmc_adc_core_ctl_offset_dac_clr_n_o => gpio_dac_clr_n_o, fmc_adc_core_ctl_offset_dac_clr_n_o => gpio_dac_clr_n_o,
fmc_adc_core_ctl_man_bitslip_o => serdes_man_bitslip, fmc_adc_core_ctl_man_bitslip_o => serdes_man_bitslip,
fmc_adc_core_ctl_test_data_en_o => test_data_en, fmc_adc_core_ctl_test_data_en_o => test_data_en,
fmc_adc_core_ctl_trig_led_o => trig_led_man,
fmc_adc_core_ctl_acq_led_o => acq_led_man,
fmc_adc_core_sta_fsm_i => acq_fsm_state, fmc_adc_core_sta_fsm_i => acq_fsm_state,
fmc_adc_core_sta_serdes_pll_i => locked_out, fmc_adc_core_sta_serdes_pll_i => locked_out,
fmc_adc_core_sta_serdes_synced_i => serdes_synced, fmc_adc_core_sta_serdes_synced_i => serdes_synced,
...@@ -632,7 +643,7 @@ begin ...@@ -632,7 +643,7 @@ begin
-- External hardware trigger synchronization -- External hardware trigger synchronization
cmp_trig_sync : ext_pulse_sync cmp_trig_sync : ext_pulse_sync
generic map( generic map(
g_MIN_PULSE_WIDTH => 5, -- clk_i ticks g_MIN_PULSE_WIDTH => 1, -- clk_i ticks
g_CLK_FREQUENCY => 100, -- MHz g_CLK_FREQUENCY => 100, -- MHz
g_OUTPUT_POLARITY => '0', -- positive pulse g_OUTPUT_POLARITY => '0', -- positive pulse
g_OUTPUT_RETRIG => false, g_OUTPUT_RETRIG => false,
...@@ -1064,7 +1075,7 @@ begin ...@@ -1064,7 +1075,7 @@ begin
end process p_wb_ddr_fifo_input; end process p_wb_ddr_fifo_input;
--wb_ddr_fifo_din <= sync_fifo_dout(63 downto 0) when single_shot = '1' else dpram_dout; --wb_ddr_fifo_din <= sync_fifo_dout(63 downto 0) when single_shot = '1' else dpram_dout;
--wb_ddr_fifo_wr_en <= samples_wr_en when single_shot = '1' else dpram_valid; --wb_ddr_fifo_wr_en <= samples_wr_en when single_shot = '1' else dpram_valid;
wb_ddr_fifo_wr <= wb_ddr_fifo_wr_en and sync_fifo_valid and not(wb_ddr_fifo_full); wb_ddr_fifo_wr <= wb_ddr_fifo_wr_en and sync_fifo_valid and not(wb_ddr_fifo_full);
wb_ddr_fifo_rd <= wb_ddr_fifo_dreq and not(wb_ddr_fifo_empty) and not(wb_ddr_stall_t); wb_ddr_fifo_rd <= wb_ddr_fifo_dreq and not(wb_ddr_fifo_empty) and not(wb_ddr_stall_t);
wb_ddr_fifo_dreq <= '1'; wb_ddr_fifo_dreq <= '1';
......
hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
View file @ ed969828
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd -- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb -- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Fri Apr 1 09:02:53 2011 -- Created : Tue Aug 30 19:24:48 2011
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
...@@ -38,6 +38,10 @@ entity fmc_adc_100Ms_csr is ...@@ -38,6 +38,10 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_ctl_man_bitslip_o : out std_logic; fmc_adc_core_ctl_man_bitslip_o : out std_logic;
-- Port for BIT field: 'Enable test data' in reg: 'Control register' -- Port for BIT field: 'Enable test data' in reg: 'Control register'
fmc_adc_core_ctl_test_data_en_o : out std_logic; fmc_adc_core_ctl_test_data_en_o : out std_logic;
-- Port for BIT field: 'Manual TRIG LED' in reg: 'Control register'
fmc_adc_core_ctl_trig_led_o : out std_logic;
-- Port for BIT field: 'Manual ACQ LED' in reg: 'Control register'
fmc_adc_core_ctl_acq_led_o : out std_logic;
-- Port for std_logic_vector field: 'State machine status' in reg: 'Status register' -- Port for std_logic_vector field: 'State machine status' in reg: 'Status register'
fmc_adc_core_sta_fsm_i : in std_logic_vector(2 downto 0); fmc_adc_core_sta_fsm_i : in std_logic_vector(2 downto 0);
-- Port for BIT field: 'SerDes PLL status' in reg: 'Status register' -- Port for BIT field: 'SerDes PLL status' in reg: 'Status register'
...@@ -114,6 +118,8 @@ signal fmc_adc_core_ctl_man_bitslip_sync0 : std_logic ; ...@@ -114,6 +118,8 @@ signal fmc_adc_core_ctl_man_bitslip_sync0 : std_logic ;
signal fmc_adc_core_ctl_man_bitslip_sync1 : std_logic ; signal fmc_adc_core_ctl_man_bitslip_sync1 : std_logic ;
signal fmc_adc_core_ctl_man_bitslip_sync2 : std_logic ; signal fmc_adc_core_ctl_man_bitslip_sync2 : std_logic ;
signal fmc_adc_core_ctl_test_data_en_int : std_logic ; signal fmc_adc_core_ctl_test_data_en_int : std_logic ;
signal fmc_adc_core_ctl_trig_led_int : std_logic ;
signal fmc_adc_core_ctl_acq_led_int : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_int : std_logic ; signal fmc_adc_core_trig_cfg_hw_trig_sel_int : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_sync0 : std_logic ; signal fmc_adc_core_trig_cfg_hw_trig_sel_sync0 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_sync1 : std_logic ; signal fmc_adc_core_trig_cfg_hw_trig_sel_sync1 : std_logic ;
...@@ -221,6 +227,8 @@ begin ...@@ -221,6 +227,8 @@ begin
fmc_adc_core_ctl_man_bitslip_int <= '0'; fmc_adc_core_ctl_man_bitslip_int <= '0';
fmc_adc_core_ctl_man_bitslip_int_delay <= '0'; fmc_adc_core_ctl_man_bitslip_int_delay <= '0';
fmc_adc_core_ctl_test_data_en_int <= '0'; fmc_adc_core_ctl_test_data_en_int <= '0';
fmc_adc_core_ctl_trig_led_int <= '0';
fmc_adc_core_ctl_acq_led_int <= '0';
fmc_adc_core_trig_cfg_hw_trig_sel_int <= '0'; fmc_adc_core_trig_cfg_hw_trig_sel_int <= '0';
fmc_adc_core_trig_cfg_ext_trig_pol_int <= '0'; fmc_adc_core_trig_cfg_ext_trig_pol_int <= '0';
fmc_adc_core_trig_cfg_hw_trig_en_int <= '0'; fmc_adc_core_trig_cfg_hw_trig_en_int <= '0';
...@@ -313,14 +321,16 @@ begin ...@@ -313,14 +321,16 @@ begin
fmc_adc_core_ctl_man_bitslip_int <= wrdata_reg(4); fmc_adc_core_ctl_man_bitslip_int <= wrdata_reg(4);
fmc_adc_core_ctl_man_bitslip_int_delay <= wrdata_reg(4); fmc_adc_core_ctl_man_bitslip_int_delay <= wrdata_reg(4);
fmc_adc_core_ctl_test_data_en_int <= wrdata_reg(5); fmc_adc_core_ctl_test_data_en_int <= wrdata_reg(5);
fmc_adc_core_ctl_trig_led_int <= wrdata_reg(6);
fmc_adc_core_ctl_acq_led_int <= wrdata_reg(7);
else else
rddata_reg(2) <= fmc_adc_core_ctl_fmc_clk_oe_int; rddata_reg(2) <= fmc_adc_core_ctl_fmc_clk_oe_int;
rddata_reg(3) <= fmc_adc_core_ctl_offset_dac_clr_n_int; rddata_reg(3) <= fmc_adc_core_ctl_offset_dac_clr_n_int;
rddata_reg(5) <= fmc_adc_core_ctl_test_data_en_int; rddata_reg(5) <= fmc_adc_core_ctl_test_data_en_int;
rddata_reg(6) <= fmc_adc_core_ctl_trig_led_int;
rddata_reg(7) <= fmc_adc_core_ctl_acq_led_int;
rddata_reg(0) <= 'X'; rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X'; rddata_reg(1) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X'; rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X'; rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X'; rddata_reg(10) <= 'X';
...@@ -842,6 +852,10 @@ begin ...@@ -842,6 +852,10 @@ begin
-- Enable test data -- Enable test data
fmc_adc_core_ctl_test_data_en_o <= fmc_adc_core_ctl_test_data_en_int; fmc_adc_core_ctl_test_data_en_o <= fmc_adc_core_ctl_test_data_en_int;
-- Manual TRIG LED
fmc_adc_core_ctl_trig_led_o <= fmc_adc_core_ctl_trig_led_int;
-- Manual ACQ LED
fmc_adc_core_ctl_acq_led_o <= fmc_adc_core_ctl_acq_led_int;
-- State machine status -- State machine status
-- SerDes PLL status -- SerDes PLL status
-- SerDes synchronization status -- SerDes synchronization status
......
hdl/adc/wb_gen/Makefile
View file @ ed969828
WBGEN2=~/wbgen2/wishbone-gen/wbgen2 WBGEN2=~/projects/wbgen2/wishbone-gen/wbgen2
RTL=../rtl/ RTL=../rtl/
fmc_adc_100Ms_csr: fmc_adc_100Ms_csr:
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
View file @ ed969828
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h * File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb * Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Wed Mar 9 11:56:09 2011 * Created : Tue Aug 30 19:24:48 2011
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
...@@ -45,6 +45,18 @@ ...@@ -45,6 +45,18 @@
/* definitions for field: Offset DACs clear (active low) in reg: Control register */ /* definitions for field: Offset DACs clear (active low) in reg: Control register */
#define FMC_ADC_CORE_CTL_OFFSET_DAC_CLR_N WBGEN2_GEN_MASK(3, 1) #define FMC_ADC_CORE_CTL_OFFSET_DAC_CLR_N WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Manual serdes bitslip in reg: Control register */
#define FMC_ADC_CORE_CTL_MAN_BITSLIP WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Enable test data in reg: Control register */
#define FMC_ADC_CORE_CTL_TEST_DATA_EN WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Manual TRIG LED in reg: Control register */
#define FMC_ADC_CORE_CTL_TRIG_LED WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Manual ACQ LED in reg: Control register */
#define FMC_ADC_CORE_CTL_ACQ_LED WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Status register */ /* definitions for register: Status register */
/* definitions for field: State machine status in reg: Status register */ /* definitions for field: State machine status in reg: Status register */
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
View file @ ed969828
...@@ -616,6 +616,40 @@ fmc_adc_core_ctl_test_data_en_o ...@@ -616,6 +616,40 @@ fmc_adc_core_ctl_test_data_en_o
wb_stb_i wb_stb_i
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ctl_trig_led_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ctl_acq_led_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
&nbsp; &nbsp;
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
...@@ -630,7 +664,7 @@ wb_stb_i ...@@ -630,7 +664,7 @@ wb_stb_i
&rarr; &rarr;
</td> </td>
<td class="td_pblock_left"> <td class="td_pblock_left">
wb_we_i fs_clk_i
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
...@@ -644,10 +678,10 @@ wb_we_i ...@@ -644,10 +678,10 @@ wb_we_i
</tr> </tr>
<tr> <tr>
<td class="td_arrow_left"> <td class="td_arrow_left">
&larr;
</td> </td>
<td class="td_pblock_left"> <td class="td_pblock_left">
wb_ack_o
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
...@@ -661,10 +695,10 @@ fmc_adc_core_sta_fsm_i[2:0] ...@@ -661,10 +695,10 @@ fmc_adc_core_sta_fsm_i[2:0]
</tr> </tr>
<tr> <tr>
<td class="td_arrow_left"> <td class="td_arrow_left">
&rarr;
</td> </td>
<td class="td_pblock_left"> <td class="td_pblock_left">
fs_clk_i
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
...@@ -2163,11 +2197,11 @@ CTL ...@@ -2163,11 +2197,11 @@ CTL
</td> </td>
</tr> </tr>
<tr> <tr>
<td class="td_unused"> <td style="border: solid 1px black;" colspan=1 class="td_field">
- ACQ_LED
</td> </td>
<td class="td_unused"> <td style="border: solid 1px black;" colspan=1 class="td_field">
- TRIG_LED
</td> </td>
<td style="border: solid 1px black;" colspan=1 class="td_field"> <td style="border: solid 1px black;" colspan=1 class="td_field">
TEST_DATA_EN TEST_DATA_EN
...@@ -2207,6 +2241,14 @@ MAN_BITSLIP ...@@ -2207,6 +2241,14 @@ MAN_BITSLIP
TEST_DATA_EN TEST_DATA_EN
</b>[<i>read/write</i>]: Enable test data </b>[<i>read/write</i>]: Enable test data
<br>Write the address counter value instead of ADC data to DDR <br>Write the address counter value instead of ADC data to DDR
<li><b>
TRIG_LED
</b>[<i>read/write</i>]: Manual TRIG LED
<br>Manual control of the front panel TRIG LED
<li><b>
ACQ_LED
</b>[<i>read/write</i>]: Manual ACQ LED
<br>Manual control of the front panel ACQ LED
</ul> </ul>
<a name="STA"></a> <a name="STA"></a>
<h3><a name="sect_3_2">3.2. Status register</a></h3> <h3><a name="sect_3_2">3.2. Status register</a></h3>
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
View file @ ed969828
...@@ -50,6 +50,24 @@ peripheral { ...@@ -50,6 +50,24 @@ peripheral {
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field {
name = "Manual TRIG LED";
description = "Manual control of the front panel TRIG LED";
prefix = "trig_led";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Manual ACQ LED";
description = "Manual control of the front panel ACQ LED";
prefix = "acq_led";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
}; };
reg { reg {
......
hdl/spec/rtl/carrier_csr.vhd
View file @ ed969828
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd -- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb -- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Wed Apr 6 12:46:12 2011 -- Created : Tue Aug 30 10:54:01 2011
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ ed969828
...@@ -139,7 +139,10 @@ entity spec_top_fmc_adc_100Ms is ...@@ -139,7 +139,10 @@ entity spec_top_fmc_adc_100Ms is
one_wire_b : inout std_logic; -- 1-wire interface (DS18B20 thermometer + unique ID) one_wire_b : inout std_logic; -- 1-wire interface (DS18B20 thermometer + unique ID)
prsnt_m2c_n_i : in std_logic -- Mezzanine present (active low) prsnt_m2c_n_i : in std_logic; -- Mezzanine present (active low)
sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
sys_sda_b : inout std_logic -- Mezzanine system I2C data (EEPROM)
); );
end spec_top_fmc_adc_100Ms; end spec_top_fmc_adc_100Ms;
...@@ -255,14 +258,14 @@ architecture rtl of spec_top_fmc_adc_100Ms is ...@@ -255,14 +258,14 @@ architecture rtl of spec_top_fmc_adc_100Ms is
adc_outb_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (even bits) adc_outb_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (even bits)
adc_outb_n_i : in std_logic_vector(3 downto 0); adc_outb_n_i : in std_logic_vector(3 downto 0);
gpio_dac_clr_n_o : out std_logic; -- offset DACs clear (active low) gpio_dac_clr_n_o : out std_logic; -- offset DACs clear (active low)
gpio_led_power_o : out std_logic; -- Mezzanine front panel power LED (PWR) gpio_led_acq_o : out std_logic; -- Mezzanine front panel power LED (PWR)
gpio_led_trigger_o : out std_logic; -- Mezzanine front panel trigger LED (TRIG) gpio_led_trig_o : out std_logic; -- Mezzanine front panel trigger LED (TRIG)
gpio_ssr_ch1_o : out std_logic_vector(6 downto 0); -- Channel 1 solid state relays control gpio_ssr_ch1_o : out std_logic_vector(6 downto 0); -- Channel 1 solid state relays control
gpio_ssr_ch2_o : out std_logic_vector(6 downto 0); -- Channel 2 solid state relays control gpio_ssr_ch2_o : out std_logic_vector(6 downto 0); -- Channel 2 solid state relays control
gpio_ssr_ch3_o : out std_logic_vector(6 downto 0); -- Channel 3 solid state relays control gpio_ssr_ch3_o : out std_logic_vector(6 downto 0); -- Channel 3 solid state relays control
gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control
gpio_si570_oe_o : out std_logic -- Si570 (programmable oscillator) output enable gpio_si570_oe_o : out std_logic -- Si570 (programmable oscillator) output enable
); );
end component fmc_adc_100Ms_core; end component fmc_adc_100Ms_core;
...@@ -382,6 +385,14 @@ architecture rtl of spec_top_fmc_adc_100Ms is ...@@ -382,6 +385,14 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal si570_sda_out : std_logic; signal si570_sda_out : std_logic;
signal si570_sda_oe_n : std_logic; signal si570_sda_oe_n : std_logic;
-- Mezzanine system I2C for EEPROM
signal sys_scl_in : std_logic;
signal sys_scl_out : std_logic;
signal sys_scl_oe_n : std_logic;
signal sys_sda_in : std_logic;
signal sys_sda_out : std_logic;
signal sys_sda_oe_n : std_logic;
-- LED control from carrier CSR register -- LED control from carrier CSR register
signal led_red : std_logic; signal led_red : std_logic;
signal led_green : std_logic; signal led_green : std_logic;
...@@ -691,7 +702,38 @@ begin ...@@ -691,7 +702,38 @@ begin
-- Mezzanine system managment I2C master -- Mezzanine system managment I2C master
-- Access to mezzanine EEPROM -- Access to mezzanine EEPROM
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_fmc_sys_i2c : wb_i2c_master
port map (
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
wb_adr_i => wb_adr(2 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_FMC_SYS_I2C * 32 + 31 downto 32 * c_CSR_WB_FMC_SYS_I2C),
wb_we_i => wb_we,
wb_stb_i => wb_stb,
wb_sel_i => wb_sel,
wb_cyc_i => wb_cyc(c_CSR_WB_FMC_SYS_I2C),
wb_ack_o => wb_ack(c_CSR_WB_FMC_SYS_I2C),
wb_int_o => open,
scl_pad_i => sys_scl_in,
scl_pad_o => sys_scl_out,
scl_padoen_o => sys_scl_oe_n,
sda_pad_i => sys_sda_in,
sda_pad_o => sys_sda_out,
sda_padoen_o => sys_sda_oe_n
);
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_FMC_SYS_I2C) <= '0';
-- Tri-state buffer for SDA and SCL
sys_scl_b <= sys_scl_out when sys_scl_oe_n = '0' else 'Z';
sys_scl_in <= sys_scl_b;
sys_sda_b <= sys_sda_out when sys_sda_oe_n = '0' else 'Z';
sys_sda_in <= sys_sda_b;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Mezzanine SPI master -- Mezzanine SPI master
...@@ -824,14 +866,14 @@ begin ...@@ -824,14 +866,14 @@ begin
adc_outb_p_i => adc_outb_p_i, adc_outb_p_i => adc_outb_p_i,
adc_outb_n_i => adc_outb_n_i, adc_outb_n_i => adc_outb_n_i,
gpio_dac_clr_n_o => gpio_dac_clr_n_o, gpio_dac_clr_n_o => gpio_dac_clr_n_o,
gpio_led_power_o => gpio_led_power_o, gpio_led_acq_o => gpio_led_power_o,
gpio_led_trigger_o => gpio_led_trigger_o, gpio_led_trig_o => gpio_led_trigger_o,
gpio_ssr_ch1_o => gpio_ssr_ch1_o, gpio_ssr_ch1_o => gpio_ssr_ch1_o,
gpio_ssr_ch2_o => gpio_ssr_ch2_o, gpio_ssr_ch2_o => gpio_ssr_ch2_o,
gpio_ssr_ch3_o => gpio_ssr_ch3_o, gpio_ssr_ch3_o => gpio_ssr_ch3_o,
gpio_ssr_ch4_o => gpio_ssr_ch4_o, gpio_ssr_ch4_o => gpio_ssr_ch4_o,
gpio_si570_oe_o => gpio_si570_oe_o gpio_si570_oe_o => gpio_si570_oe_o
); );
-- Classic slave supporting single pipelined accesses, stall isn't used -- Classic slave supporting single pipelined accesses, stall isn't used
......
hdl/spec/spec_top_fmc_adc_100Ms.ucf
View file @ ed969828
...@@ -58,14 +58,6 @@ NET "clk20_vcxo_i" IOSTANDARD = "LVCMOS25"; ...@@ -58,14 +58,6 @@ NET "clk20_vcxo_i" IOSTANDARD = "LVCMOS25";
#NET "THERMO_ID" LOC = D4; #NET "THERMO_ID" LOC = D4;
#NET "THERMO_ID" IOSTANDARD = "LVCMOS25"; #NET "THERMO_ID" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# I2C interface
#----------------------------------------
#NET "FPGA_SCL" LOC = F7;
#NET "FPGA_SCL" IOSTANDARD = "LVCMOS25";
#NET "FPGA_SDA" LOC = F8;
#NET "FPGA_SDA" IOSTANDARD = "LVCMOS25";
#---------------------------------------- #----------------------------------------
# GN4124 interface # GN4124 interface
#---------------------------------------- #----------------------------------------
...@@ -345,6 +337,12 @@ NET "one_wire_b" IOSTANDARD = "LVCMOS25"; ...@@ -345,6 +337,12 @@ NET "one_wire_b" IOSTANDARD = "LVCMOS25";
NET "prsnt_m2c_n_i" LOC = AB14; # PRSNT_M2C_L NET "prsnt_m2c_n_i" LOC = AB14; # PRSNT_M2C_L
NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25"; NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "sys_scl_b" LOC = F7; # SCL
NET "sys_scl_b" IOSTANDARD = "LVCMOS25";
NET "sys_sda_b" LOC = F8; # SDA
NET "sys_sda_b" IOSTANDARD = "LVCMOS25";
#---------------------------------------- #----------------------------------------
# FMC slot (unused pins) # FMC slot (unused pins)
#---------------------------------------- #----------------------------------------
......
hdl/spec/wb_gen/Makefile
View file @ ed969828
WBGEN2=~/wbgen2/wishbone-gen/wbgen2 WBGEN2=~/projects/wbgen2/wishbone-gen/wbgen2
RTL=../rtl/ RTL=../rtl/
carrier_csr: carrier_csr:
......
hdl/spec/wb_gen/carrier_csr.h
View file @ ed969828
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : carrier_csr.h * File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb * Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Wed Apr 6 12:46:12 2011 * Created : Tue Aug 30 10:54:01 2011
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......
hdl/spec/wb_gen/carrier_csr.htm
View file @ ed969828
...@@ -1545,7 +1545,7 @@ FMC_PRES ...@@ -1545,7 +1545,7 @@ FMC_PRES
<li><b> <li><b>
FMC_PRES FMC_PRES
</b>[<i>read-only</i>]: FMC presence </b>[<i>read-only</i>]: FMC presence
<br>0: FMC slot is not populated<br>1: FMC slot is populated <br>0: FMC slot is populated<br>1: FMC slot is not populated
<li><b> <li><b>
P2L_PLL_LCK P2L_PLL_LCK
</b>[<i>read-only</i>]: GN4142 core P2L PLL status </b>[<i>read-only</i>]: GN4142 core P2L PLL status
......
hdl/spec/wb_gen/carrier_csr.wb
View file @ ed969828
...@@ -74,7 +74,7 @@ peripheral { ...@@ -74,7 +74,7 @@ peripheral {
field { field {
name = "FMC presence"; name = "FMC presence";
description = "0: FMC slot is not populated\n1: FMC slot is populated"; description = "0: FMC slot is populated\n1: FMC slot is not populated";
prefix = "fmc_pres"; prefix = "fmc_pres";
type = BIT; type = BIT;
access_bus = READ_ONLY; access_bus = READ_ONLY;
......
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