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FMC ADC 100M 14b 4cha - Gateware
Commit e7e2f3c9 authored by mcattin's avatar mcattin
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Remove utc registers. Add trigger address, gain and offset calibration registers. 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@92 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent 9f574761
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Showing with 1363 additions and 1026 deletions
hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
View file @ e7e2f3c9
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Thu Nov 3 17:06:56 2011
-- Created : Wed Nov 23 14:38:25 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -42,12 +42,16 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_ctl_trig_led_o : out std_logic;
-- Port for BIT field: 'Manual ACQ LED' in reg: 'Control register'
fmc_adc_core_ctl_acq_led_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Control register'
fmc_adc_core_ctl_reserved_o : out std_logic_vector(23 downto 0);
-- Port for std_logic_vector field: 'State machine status' in reg: 'Status register'
fmc_adc_core_sta_fsm_i : in std_logic_vector(2 downto 0);
-- Port for BIT field: 'SerDes PLL status' in reg: 'Status register'
fmc_adc_core_sta_serdes_pll_i : in std_logic;
-- Port for BIT field: 'SerDes synchronization status' in reg: 'Status register'
fmc_adc_core_sta_serdes_synced_i : in std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Status register'
fmc_adc_core_sta_reserved_i : in std_logic_vector(26 downto 0);
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger selection' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_hw_trig_sel_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'External hardware trigger polarity' in reg: 'Trigger configuration'
......@@ -58,8 +62,8 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_trig_cfg_sw_trig_en_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel selection for internal trigger' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_int_trig_sel_o : out std_logic_vector(1 downto 0);
-- Port for std_logic_vector field: 'Dummy' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_dummy_o : out std_logic_vector(9 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_reserved_o : out std_logic_vector(9 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Threshold for internal trigger' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_int_trig_thres_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Trigger delay value' in reg: 'Trigger delay'
......@@ -69,20 +73,24 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_sw_trig_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Number of shots' in reg: 'Number of shots'
fmc_adc_core_shots_nb_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Trigger UTC tag (LSBs)' in reg: 'Trigger UTC tag (LSBs)'
fmc_adc_core_trig_utc_l_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Trigger UTC tag (MSBs)' in reg: 'Trigger UTC tag (MSBs)'
fmc_adc_core_trig_utc_h_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Start UTC tag (LSBs)' in reg: 'Start UTC tag (LSBs)'
fmc_adc_core_start_utc_l_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Start UTC tag (MSBs)' in reg: 'Start UTC tag (MSBs)'
fmc_adc_core_start_utc_h_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Stop UTC tag (LSBs)' in reg: 'Stop UTC tag (LSBs)'
fmc_adc_core_stop_utc_l_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Stop UTC tag (MSBs)' in reg: 'Stop UTC tag (MSBs)'
fmc_adc_core_stop_utc_h_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Number of shots'
fmc_adc_core_shots_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Trigger address' in reg: 'Trigger address register'
fmc_adc_core_trig_pos_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Gain calibration' in reg: 'Gain calibration register'
fmc_adc_core_gain_cal_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Offset calibration' in reg: 'Offset calibration register'
fmc_adc_core_offset_cal_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Reserved register'
fmc_adc_core_reserved_0_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Reserved register'
fmc_adc_core_reserved_1_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Reserved register'
fmc_adc_core_reserved_2_i : in std_logic_vector(31 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Sample rate decimation' in reg: 'Sample rate'
fmc_adc_core_sr_deci_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Sample rate'
fmc_adc_core_sr_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Pre-trigger samples' in reg: 'Pre-trigger samples'
fmc_adc_core_pre_samples_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Post-trigger samples' in reg: 'Post-trigger samples'
......@@ -91,20 +99,36 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_samp_cnt_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 1' in reg: 'Solid state relays control for channel 1'
fmc_adc_core_ch1_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Solid state relays control for channel 1'
fmc_adc_core_ch1_reserved_o : out std_logic_vector(24 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 1 current value' in reg: 'Channel 1 current value'
fmc_adc_core_ch1_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 1 current value'
fmc_adc_core_ch1_reserved_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 2' in reg: 'Solid state relays control for channel 2'
fmc_adc_core_ch2_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Solid state relays control for channel 2'
fmc_adc_core_ch2_reserved_o : out std_logic_vector(24 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 2 current value' in reg: 'Channel 2 current value'
fmc_adc_core_ch2_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 2 current value'
fmc_adc_core_ch2_reserved_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 3' in reg: 'Solid state relays control for channel 3'
fmc_adc_core_ch3_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Solid state relays control for channel 3'
fmc_adc_core_ch3_reserved_o : out std_logic_vector(24 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 3 current value' in reg: 'Channel 3 current value'
fmc_adc_core_ch3_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 3 current value'
fmc_adc_core_ch3_reserved_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 4' in reg: 'Solid state relays control for channel 4'
fmc_adc_core_ch4_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Solid state relays control for channel 4'
fmc_adc_core_ch4_reserved_o : out std_logic_vector(24 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 4 current value' in reg: 'Channel 4 current value'
fmc_adc_core_ch4_val_i : in std_logic_vector(15 downto 0)
fmc_adc_core_ch4_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 4 current value'
fmc_adc_core_ch4_reserved_i : in std_logic_vector(15 downto 0)
);
end fmc_adc_100Ms_csr;
......@@ -120,6 +144,7 @@ signal fmc_adc_core_ctl_man_bitslip_sync2 : std_logic ;
signal fmc_adc_core_ctl_test_data_en_int : std_logic ;
signal fmc_adc_core_ctl_trig_led_int : std_logic ;
signal fmc_adc_core_ctl_acq_led_int : std_logic ;
signal fmc_adc_core_ctl_reserved_int : std_logic_vector(23 downto 0);
signal fmc_adc_core_trig_cfg_hw_trig_sel_int : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_sync0 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_sync1 : std_logic ;
......@@ -138,7 +163,7 @@ signal fmc_adc_core_trig_cfg_int_trig_sel_swb_delay : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_sel_swb_s0 : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_sel_swb_s1 : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_sel_swb_s2 : std_logic ;
signal fmc_adc_core_trig_cfg_dummy_int : std_logic_vector(9 downto 0);
signal fmc_adc_core_trig_cfg_reserved_int : std_logic_vector(9 downto 0);
signal fmc_adc_core_trig_cfg_int_trig_thres_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_trig_cfg_int_trig_thres_swb : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_thres_swb_delay : std_logic ;
......@@ -152,15 +177,20 @@ signal fmc_adc_core_sw_trig_wr_sync0 : std_logic ;
signal fmc_adc_core_sw_trig_wr_sync1 : std_logic ;
signal fmc_adc_core_sw_trig_wr_sync2 : std_logic ;
signal fmc_adc_core_shots_nb_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_shots_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_gain_cal_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_offset_cal_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_sr_deci_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_sr_deci_swb : std_logic ;
signal fmc_adc_core_sr_deci_swb_delay : std_logic ;
signal fmc_adc_core_sr_deci_swb_s0 : std_logic ;
signal fmc_adc_core_sr_deci_swb_s1 : std_logic ;
signal fmc_adc_core_sr_deci_swb_s2 : std_logic ;
signal fmc_adc_core_sr_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_pre_samples_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_post_samples_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_ch1_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch1_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch1_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch1_val_lwb : std_logic ;
signal fmc_adc_core_ch1_val_lwb_delay : std_logic ;
......@@ -169,6 +199,7 @@ signal fmc_adc_core_ch1_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch1_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch1_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch2_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch2_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch2_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch2_val_lwb : std_logic ;
signal fmc_adc_core_ch2_val_lwb_delay : std_logic ;
......@@ -177,6 +208,7 @@ signal fmc_adc_core_ch2_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch2_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch2_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch3_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch3_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch3_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch3_val_lwb : std_logic ;
signal fmc_adc_core_ch3_val_lwb_delay : std_logic ;
......@@ -185,6 +217,7 @@ signal fmc_adc_core_ch3_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch3_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch3_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch4_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch4_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch4_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch4_val_lwb : std_logic ;
signal fmc_adc_core_ch4_val_lwb_delay : std_logic ;
......@@ -229,6 +262,7 @@ begin
fmc_adc_core_ctl_test_data_en_int <= '0';
fmc_adc_core_ctl_trig_led_int <= '0';
fmc_adc_core_ctl_acq_led_int <= '0';
fmc_adc_core_ctl_reserved_int <= "000000000000000000000000";
fmc_adc_core_trig_cfg_hw_trig_sel_int <= '0';
fmc_adc_core_trig_cfg_ext_trig_pol_int <= '0';
fmc_adc_core_trig_cfg_hw_trig_en_int <= '0';
......@@ -236,7 +270,7 @@ begin
fmc_adc_core_trig_cfg_int_trig_sel_int <= "00";
fmc_adc_core_trig_cfg_int_trig_sel_swb <= '0';
fmc_adc_core_trig_cfg_int_trig_sel_swb_delay <= '0';
fmc_adc_core_trig_cfg_dummy_int <= "0000000000";
fmc_adc_core_trig_cfg_reserved_int <= "0000000000";
fmc_adc_core_trig_cfg_int_trig_thres_int <= "0000000000000000";
fmc_adc_core_trig_cfg_int_trig_thres_swb <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_swb_delay <= '0';
......@@ -244,24 +278,32 @@ begin
fmc_adc_core_sw_trig_wr_int <= '0';
fmc_adc_core_sw_trig_wr_int_delay <= '0';
fmc_adc_core_shots_nb_int <= "0000000000000000";
fmc_adc_core_shots_reserved_int <= "0000000000000000";
fmc_adc_core_gain_cal_int <= "00000000000000000000000000000000";
fmc_adc_core_offset_cal_int <= "00000000000000000000000000000000";
fmc_adc_core_sr_deci_int <= "0000000000000000";
fmc_adc_core_sr_deci_swb <= '0';
fmc_adc_core_sr_deci_swb_delay <= '0';
fmc_adc_core_sr_reserved_int <= "0000000000000000";
fmc_adc_core_pre_samples_int <= "00000000000000000000000000000000";
fmc_adc_core_post_samples_int <= "00000000000000000000000000000000";
fmc_adc_core_ch1_ssr_int <= "0000000";
fmc_adc_core_ch1_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch1_val_lwb <= '0';
fmc_adc_core_ch1_val_lwb_delay <= '0';
fmc_adc_core_ch1_val_lwb_in_progress <= '0';
fmc_adc_core_ch2_ssr_int <= "0000000";
fmc_adc_core_ch2_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch2_val_lwb <= '0';
fmc_adc_core_ch2_val_lwb_delay <= '0';
fmc_adc_core_ch2_val_lwb_in_progress <= '0';
fmc_adc_core_ch3_ssr_int <= "0000000";
fmc_adc_core_ch3_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch3_val_lwb <= '0';
fmc_adc_core_ch3_val_lwb_delay <= '0';
fmc_adc_core_ch3_val_lwb_in_progress <= '0';
fmc_adc_core_ch4_ssr_int <= "0000000";
fmc_adc_core_ch4_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch4_val_lwb <= '0';
fmc_adc_core_ch4_val_lwb_delay <= '0';
fmc_adc_core_ch4_val_lwb_in_progress <= '0';
......@@ -323,38 +365,16 @@ begin
fmc_adc_core_ctl_test_data_en_int <= wrdata_reg(5);
fmc_adc_core_ctl_trig_led_int <= wrdata_reg(6);
fmc_adc_core_ctl_acq_led_int <= wrdata_reg(7);
fmc_adc_core_ctl_reserved_int <= wrdata_reg(31 downto 8);
else
rddata_reg(2) <= fmc_adc_core_ctl_fmc_clk_oe_int;
rddata_reg(3) <= fmc_adc_core_ctl_offset_dac_clr_n_int;
rddata_reg(5) <= fmc_adc_core_ctl_test_data_en_int;
rddata_reg(6) <= fmc_adc_core_ctl_trig_led_int;
rddata_reg(7) <= fmc_adc_core_ctl_acq_led_int;
rddata_reg(31 downto 8) <= fmc_adc_core_ctl_reserved_int;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(4) <= '1';
ack_in_progress <= '1';
......@@ -364,33 +384,7 @@ begin
rddata_reg(2 downto 0) <= fmc_adc_core_sta_fsm_i;
rddata_reg(3) <= fmc_adc_core_sta_serdes_pll_i;
rddata_reg(4) <= fmc_adc_core_sta_serdes_synced_i;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(31 downto 5) <= fmc_adc_core_sta_reserved_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
......@@ -403,7 +397,7 @@ begin
fmc_adc_core_trig_cfg_int_trig_sel_int <= wrdata_reg(5 downto 4);
fmc_adc_core_trig_cfg_int_trig_sel_swb <= '1';
fmc_adc_core_trig_cfg_int_trig_sel_swb_delay <= '1';
fmc_adc_core_trig_cfg_dummy_int <= wrdata_reg(15 downto 6);
fmc_adc_core_trig_cfg_reserved_int <= wrdata_reg(15 downto 6);
fmc_adc_core_trig_cfg_int_trig_thres_int <= wrdata_reg(31 downto 16);
fmc_adc_core_trig_cfg_int_trig_thres_swb <= '1';
fmc_adc_core_trig_cfg_int_trig_thres_swb_delay <= '1';
......@@ -413,7 +407,7 @@ begin
rddata_reg(2) <= fmc_adc_core_trig_cfg_hw_trig_en_int;
rddata_reg(3) <= fmc_adc_core_trig_cfg_sw_trig_en_int;
rddata_reg(5 downto 4) <= fmc_adc_core_trig_cfg_int_trig_sel_int;
rddata_reg(15 downto 6) <= fmc_adc_core_trig_cfg_dummy_int;
rddata_reg(15 downto 6) <= fmc_adc_core_trig_cfg_reserved_int;
rddata_reg(31 downto 16) <= fmc_adc_core_trig_cfg_int_trig_thres_int;
end if;
ack_sreg(3) <= '1';
......@@ -469,66 +463,54 @@ begin
when "00101" =>
if (wb_we_i = '1') then
fmc_adc_core_shots_nb_int <= wrdata_reg(15 downto 0);
fmc_adc_core_shots_reserved_int <= wrdata_reg(31 downto 16);
else
rddata_reg(15 downto 0) <= fmc_adc_core_shots_nb_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(31 downto 16) <= fmc_adc_core_shots_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= fmc_adc_core_trig_utc_l_i;
rddata_reg(31 downto 0) <= fmc_adc_core_trig_pos_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111" =>
if (wb_we_i = '1') then
fmc_adc_core_gain_cal_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= fmc_adc_core_trig_utc_h_i;
rddata_reg(31 downto 0) <= fmc_adc_core_gain_cal_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000" =>
if (wb_we_i = '1') then
fmc_adc_core_offset_cal_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= fmc_adc_core_start_utc_l_i;
rddata_reg(31 downto 0) <= fmc_adc_core_offset_cal_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= fmc_adc_core_start_utc_h_i;
rddata_reg(31 downto 0) <= fmc_adc_core_reserved_0_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= fmc_adc_core_stop_utc_l_i;
rddata_reg(31 downto 0) <= fmc_adc_core_reserved_1_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= fmc_adc_core_stop_utc_h_i;
rddata_reg(31 downto 0) <= fmc_adc_core_reserved_2_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
......@@ -537,24 +519,10 @@ begin
fmc_adc_core_sr_deci_int <= wrdata_reg(15 downto 0);
fmc_adc_core_sr_deci_swb <= '1';
fmc_adc_core_sr_deci_swb_delay <= '1';
fmc_adc_core_sr_reserved_int <= wrdata_reg(31 downto 16);
else
rddata_reg(15 downto 0) <= fmc_adc_core_sr_deci_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(31 downto 16) <= fmc_adc_core_sr_reserved_int;
end if;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
......@@ -584,33 +552,10 @@ begin
when "10000" =>
if (wb_we_i = '1') then
fmc_adc_core_ch1_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch1_reserved_int <= wrdata_reg(31 downto 7);
else
rddata_reg(6 downto 0) <= fmc_adc_core_ch1_ssr_int;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(31 downto 7) <= fmc_adc_core_ch1_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
......@@ -620,55 +565,17 @@ begin
fmc_adc_core_ch1_val_lwb <= '1';
fmc_adc_core_ch1_val_lwb_delay <= '1';
fmc_adc_core_ch1_val_lwb_in_progress <= '1';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(31 downto 16) <= fmc_adc_core_ch1_reserved_i;
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10010" =>
if (wb_we_i = '1') then
fmc_adc_core_ch2_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch2_reserved_int <= wrdata_reg(31 downto 7);
else
rddata_reg(6 downto 0) <= fmc_adc_core_ch2_ssr_int;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(31 downto 7) <= fmc_adc_core_ch2_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
......@@ -678,55 +585,17 @@ begin
fmc_adc_core_ch2_val_lwb <= '1';
fmc_adc_core_ch2_val_lwb_delay <= '1';
fmc_adc_core_ch2_val_lwb_in_progress <= '1';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(31 downto 16) <= fmc_adc_core_ch2_reserved_i;
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10100" =>
if (wb_we_i = '1') then
fmc_adc_core_ch3_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch3_reserved_int <= wrdata_reg(31 downto 7);
else
rddata_reg(6 downto 0) <= fmc_adc_core_ch3_ssr_int;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(31 downto 7) <= fmc_adc_core_ch3_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
......@@ -736,55 +605,17 @@ begin
fmc_adc_core_ch3_val_lwb <= '1';
fmc_adc_core_ch3_val_lwb_delay <= '1';
fmc_adc_core_ch3_val_lwb_in_progress <= '1';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(31 downto 16) <= fmc_adc_core_ch3_reserved_i;
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10110" =>
if (wb_we_i = '1') then
fmc_adc_core_ch4_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch4_reserved_int <= wrdata_reg(31 downto 7);
else
rddata_reg(6 downto 0) <= fmc_adc_core_ch4_ssr_int;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(31 downto 7) <= fmc_adc_core_ch4_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
......@@ -794,22 +625,7 @@ begin
fmc_adc_core_ch4_val_lwb <= '1';
fmc_adc_core_ch4_val_lwb_delay <= '1';
fmc_adc_core_ch4_val_lwb_in_progress <= '1';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(31 downto 16) <= fmc_adc_core_ch4_reserved_i;
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
......@@ -856,9 +672,12 @@ begin
fmc_adc_core_ctl_trig_led_o <= fmc_adc_core_ctl_trig_led_int;
-- Manual ACQ LED
fmc_adc_core_ctl_acq_led_o <= fmc_adc_core_ctl_acq_led_int;
-- Reserved
fmc_adc_core_ctl_reserved_o <= fmc_adc_core_ctl_reserved_int;
-- State machine status
-- SerDes PLL status
-- SerDes synchronization status
-- Reserved
-- Hardware trigger selection
-- synchronizer chain for field : Hardware trigger selection (type RW/RO, bus_clock_int <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
......@@ -943,8 +762,8 @@ begin
end process;
-- Dummy
fmc_adc_core_trig_cfg_dummy_o <= fmc_adc_core_trig_cfg_dummy_int;
-- Reserved
fmc_adc_core_trig_cfg_reserved_o <= fmc_adc_core_trig_cfg_reserved_int;
-- Threshold for internal trigger
-- asynchronous std_logic_vector register : Threshold for internal trigger (type RW/RO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
......@@ -987,12 +806,16 @@ begin
-- Number of shots
fmc_adc_core_shots_nb_o <= fmc_adc_core_shots_nb_int;
-- Trigger UTC tag (LSBs)
-- Trigger UTC tag (MSBs)
-- Start UTC tag (LSBs)
-- Start UTC tag (MSBs)
-- Stop UTC tag (LSBs)
-- Stop UTC tag (MSBs)
-- Reserved
fmc_adc_core_shots_reserved_o <= fmc_adc_core_shots_reserved_int;
-- Trigger address
-- Gain calibration
fmc_adc_core_gain_cal_o <= fmc_adc_core_gain_cal_int;
-- Offset calibration
fmc_adc_core_offset_cal_o <= fmc_adc_core_offset_cal_int;
-- Reserved
-- Reserved
-- Reserved
-- Sample rate decimation
-- asynchronous std_logic_vector register : Sample rate decimation (type RW/RO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
......@@ -1013,6 +836,8 @@ begin
end process;
-- Reserved
fmc_adc_core_sr_reserved_o <= fmc_adc_core_sr_reserved_int;
-- Pre-trigger samples
fmc_adc_core_pre_samples_o <= fmc_adc_core_pre_samples_int;
-- Post-trigger samples
......@@ -1020,6 +845,8 @@ begin
-- Sample counter
-- Solid state relays control for channel 1
fmc_adc_core_ch1_ssr_o <= fmc_adc_core_ch1_ssr_int;
-- Reserved
fmc_adc_core_ch1_reserved_o <= fmc_adc_core_ch1_reserved_int;
-- Channel 1 current value
-- asynchronous std_logic_vector register : Channel 1 current value (type RO/WO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
......@@ -1040,8 +867,11 @@ begin
end process;
-- Reserved
-- Solid state relays control for channel 2
fmc_adc_core_ch2_ssr_o <= fmc_adc_core_ch2_ssr_int;
-- Reserved
fmc_adc_core_ch2_reserved_o <= fmc_adc_core_ch2_reserved_int;
-- Channel 2 current value
-- asynchronous std_logic_vector register : Channel 2 current value (type RO/WO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
......@@ -1062,8 +892,11 @@ begin
end process;
-- Reserved
-- Solid state relays control for channel 3
fmc_adc_core_ch3_ssr_o <= fmc_adc_core_ch3_ssr_int;
-- Reserved
fmc_adc_core_ch3_reserved_o <= fmc_adc_core_ch3_reserved_int;
-- Channel 3 current value
-- asynchronous std_logic_vector register : Channel 3 current value (type RO/WO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
......@@ -1084,8 +917,11 @@ begin
end process;
-- Reserved
-- Solid state relays control for channel 4
fmc_adc_core_ch4_ssr_o <= fmc_adc_core_ch4_ssr_int;
-- Reserved
fmc_adc_core_ch4_reserved_o <= fmc_adc_core_ch4_reserved_int;
-- Channel 4 current value
-- asynchronous std_logic_vector register : Channel 4 current value (type RO/WO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
......@@ -1106,6 +942,7 @@ begin
end process;
-- Reserved
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
View file @ e7e2f3c9
......@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Thu Nov 3 17:06:57 2011
* Created : Wed Nov 23 14:38:25 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -57,6 +57,12 @@
/* definitions for field: Manual ACQ LED in reg: Control register */
#define FMC_ADC_CORE_CTL_ACQ_LED WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Reserved in reg: Control register */
#define FMC_ADC_CORE_CTL_RESERVED_MASK WBGEN2_GEN_MASK(8, 24)
#define FMC_ADC_CORE_CTL_RESERVED_SHIFT 8
#define FMC_ADC_CORE_CTL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 8, 24)
#define FMC_ADC_CORE_CTL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 8, 24)
/* definitions for register: Status register */
/* definitions for field: State machine status in reg: Status register */
......@@ -71,6 +77,12 @@
/* definitions for field: SerDes synchronization status in reg: Status register */
#define FMC_ADC_CORE_STA_SERDES_SYNCED WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Reserved in reg: Status register */
#define FMC_ADC_CORE_STA_RESERVED_MASK WBGEN2_GEN_MASK(5, 27)
#define FMC_ADC_CORE_STA_RESERVED_SHIFT 5
#define FMC_ADC_CORE_STA_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 27)
#define FMC_ADC_CORE_STA_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 5, 27)
/* definitions for register: Trigger configuration */
/* definitions for field: Hardware trigger selection in reg: Trigger configuration */
......@@ -91,11 +103,11 @@
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_W(value) WBGEN2_GEN_WRITE(value, 4, 2)
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_R(reg) WBGEN2_GEN_READ(reg, 4, 2)
/* definitions for field: Dummy in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_DUMMY_MASK WBGEN2_GEN_MASK(6, 10)
#define FMC_ADC_CORE_TRIG_CFG_DUMMY_SHIFT 6
#define FMC_ADC_CORE_TRIG_CFG_DUMMY_W(value) WBGEN2_GEN_WRITE(value, 6, 10)
#define FMC_ADC_CORE_TRIG_CFG_DUMMY_R(reg) WBGEN2_GEN_READ(reg, 6, 10)
/* definitions for field: Reserved in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_RESERVED_MASK WBGEN2_GEN_MASK(6, 10)
#define FMC_ADC_CORE_TRIG_CFG_RESERVED_SHIFT 6
#define FMC_ADC_CORE_TRIG_CFG_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 6, 10)
#define FMC_ADC_CORE_TRIG_CFG_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 6, 10)
/* definitions for field: Threshold for internal trigger in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_THRES_MASK WBGEN2_GEN_MASK(16, 16)
......@@ -115,17 +127,23 @@
#define FMC_ADC_CORE_SHOTS_NB_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_SHOTS_NB_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Trigger UTC tag (LSBs) */
/* definitions for field: Reserved in reg: Number of shots */
#define FMC_ADC_CORE_SHOTS_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_SHOTS_RESERVED_SHIFT 16
#define FMC_ADC_CORE_SHOTS_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_SHOTS_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Trigger address register */
/* definitions for register: Trigger UTC tag (MSBs) */
/* definitions for register: Gain calibration register */
/* definitions for register: Start UTC tag (LSBs) */
/* definitions for register: Offset calibration register */
/* definitions for register: Start UTC tag (MSBs) */
/* definitions for register: Reserved register */
/* definitions for register: Stop UTC tag (LSBs) */
/* definitions for register: Reserved register */
/* definitions for register: Stop UTC tag (MSBs) */
/* definitions for register: Reserved register */
/* definitions for register: Sample rate */
......@@ -135,6 +153,12 @@
#define FMC_ADC_CORE_SR_DECI_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_SR_DECI_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Sample rate */
#define FMC_ADC_CORE_SR_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_SR_RESERVED_SHIFT 16
#define FMC_ADC_CORE_SR_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_SR_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Pre-trigger samples */
/* definitions for register: Post-trigger samples */
......@@ -143,20 +167,116 @@
/* definitions for register: Solid state relays control for channel 1 */
/* definitions for field: Solid state relays control for channel 1 in reg: Solid state relays control for channel 1 */
#define FMC_ADC_CORE_CH1_SSR_MASK WBGEN2_GEN_MASK(0, 7)
#define FMC_ADC_CORE_CH1_SSR_SHIFT 0
#define FMC_ADC_CORE_CH1_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_CORE_CH1_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for field: Reserved in reg: Solid state relays control for channel 1 */
#define FMC_ADC_CORE_CH1_RESERVED_MASK WBGEN2_GEN_MASK(7, 25)
#define FMC_ADC_CORE_CH1_RESERVED_SHIFT 7
#define FMC_ADC_CORE_CH1_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 7, 25)
#define FMC_ADC_CORE_CH1_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 7, 25)
/* definitions for register: Channel 1 current value */
/* definitions for field: Channel 1 current value in reg: Channel 1 current value */
#define FMC_ADC_CORE_CH1_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH1_VAL_SHIFT 0
#define FMC_ADC_CORE_CH1_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH1_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 1 current value */
#define FMC_ADC_CORE_CH1_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH1_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH1_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH1_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Solid state relays control for channel 2 */
/* definitions for field: Solid state relays control for channel 2 in reg: Solid state relays control for channel 2 */
#define FMC_ADC_CORE_CH2_SSR_MASK WBGEN2_GEN_MASK(0, 7)
#define FMC_ADC_CORE_CH2_SSR_SHIFT 0
#define FMC_ADC_CORE_CH2_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_CORE_CH2_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for field: Reserved in reg: Solid state relays control for channel 2 */
#define FMC_ADC_CORE_CH2_RESERVED_MASK WBGEN2_GEN_MASK(7, 25)
#define FMC_ADC_CORE_CH2_RESERVED_SHIFT 7
#define FMC_ADC_CORE_CH2_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 7, 25)
#define FMC_ADC_CORE_CH2_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 7, 25)
/* definitions for register: Channel 2 current value */
/* definitions for field: Channel 2 current value in reg: Channel 2 current value */
#define FMC_ADC_CORE_CH2_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH2_VAL_SHIFT 0
#define FMC_ADC_CORE_CH2_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH2_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 2 current value */
#define FMC_ADC_CORE_CH2_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH2_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH2_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH2_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Solid state relays control for channel 3 */
/* definitions for field: Solid state relays control for channel 3 in reg: Solid state relays control for channel 3 */
#define FMC_ADC_CORE_CH3_SSR_MASK WBGEN2_GEN_MASK(0, 7)
#define FMC_ADC_CORE_CH3_SSR_SHIFT 0
#define FMC_ADC_CORE_CH3_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_CORE_CH3_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for field: Reserved in reg: Solid state relays control for channel 3 */
#define FMC_ADC_CORE_CH3_RESERVED_MASK WBGEN2_GEN_MASK(7, 25)
#define FMC_ADC_CORE_CH3_RESERVED_SHIFT 7
#define FMC_ADC_CORE_CH3_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 7, 25)
#define FMC_ADC_CORE_CH3_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 7, 25)
/* definitions for register: Channel 3 current value */
/* definitions for field: Channel 3 current value in reg: Channel 3 current value */
#define FMC_ADC_CORE_CH3_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH3_VAL_SHIFT 0
#define FMC_ADC_CORE_CH3_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH3_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 3 current value */
#define FMC_ADC_CORE_CH3_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH3_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH3_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH3_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Solid state relays control for channel 4 */
/* definitions for field: Solid state relays control for channel 4 in reg: Solid state relays control for channel 4 */
#define FMC_ADC_CORE_CH4_SSR_MASK WBGEN2_GEN_MASK(0, 7)
#define FMC_ADC_CORE_CH4_SSR_SHIFT 0
#define FMC_ADC_CORE_CH4_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_CORE_CH4_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for field: Reserved in reg: Solid state relays control for channel 4 */
#define FMC_ADC_CORE_CH4_RESERVED_MASK WBGEN2_GEN_MASK(7, 25)
#define FMC_ADC_CORE_CH4_RESERVED_SHIFT 7
#define FMC_ADC_CORE_CH4_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 7, 25)
#define FMC_ADC_CORE_CH4_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 7, 25)
/* definitions for register: Channel 4 current value */
/* definitions for field: Channel 4 current value in reg: Channel 4 current value */
#define FMC_ADC_CORE_CH4_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH4_VAL_SHIFT 0
#define FMC_ADC_CORE_CH4_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH4_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 4 current value */
#define FMC_ADC_CORE_CH4_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH4_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH4_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH4_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
PACKED struct FMC_ADC_CORE_WB {
/* [0x0]: REG Control register */
uint32_t CTL;
......@@ -170,18 +290,18 @@ PACKED struct FMC_ADC_CORE_WB {
uint32_t SW_TRIG;
/* [0x14]: REG Number of shots */
uint32_t SHOTS;
/* [0x18]: REG Trigger UTC tag (LSBs) */
uint32_t TRIG_UTC_L;
/* [0x1c]: REG Trigger UTC tag (MSBs) */
uint32_t TRIG_UTC_H;
/* [0x20]: REG Start UTC tag (LSBs) */
uint32_t START_UTC_L;
/* [0x24]: REG Start UTC tag (MSBs) */
uint32_t START_UTC_H;
/* [0x28]: REG Stop UTC tag (LSBs) */
uint32_t STOP_UTC_L;
/* [0x2c]: REG Stop UTC tag (MSBs) */
uint32_t STOP_UTC_H;
/* [0x18]: REG Trigger address register */
uint32_t TRIG_POS;
/* [0x1c]: REG Gain calibration register */
uint32_t GAIN_CAL;
/* [0x20]: REG Offset calibration register */
uint32_t OFFSET_CAL;
/* [0x24]: REG Reserved register */
uint32_t RESERVED_0;
/* [0x28]: REG Reserved register */
uint32_t RESERVED_1;
/* [0x2c]: REG Reserved register */
uint32_t RESERVED_2;
/* [0x30]: REG Sample rate */
uint32_t SR;
/* [0x34]: REG Pre-trigger samples */
......@@ -191,21 +311,21 @@ PACKED struct FMC_ADC_CORE_WB {
/* [0x3c]: REG Sample counter */
uint32_t SAMP_CNT;
/* [0x40]: REG Solid state relays control for channel 1 */
uint32_t CH1_SSR;
uint32_t CH1;
/* [0x44]: REG Channel 1 current value */
uint32_t CH1_VAL;
uint32_t CH1;
/* [0x48]: REG Solid state relays control for channel 2 */
uint32_t CH2_SSR;
uint32_t CH2;
/* [0x4c]: REG Channel 2 current value */
uint32_t CH2_VAL;
uint32_t CH2;
/* [0x50]: REG Solid state relays control for channel 3 */
uint32_t CH3_SSR;
uint32_t CH3;
/* [0x54]: REG Channel 3 current value */
uint32_t CH3_VAL;
uint32_t CH3;
/* [0x58]: REG Solid state relays control for channel 4 */
uint32_t CH4_SSR;
uint32_t CH4;
/* [0x5c]: REG Channel 4 current value */
uint32_t CH4_VAL;
uint32_t CH4;
};
#endif
hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
View file @ e7e2f3c9
......@@ -40,12 +40,12 @@
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Trigger delay</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">Software trigger</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">Number of shots</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">Trigger UTC tag (LSBs)</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">Trigger UTC tag (MSBs)</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">Start UTC tag (LSBs)</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">Start UTC tag (MSBs)</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">Stop UTC tag (LSBs)</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">Stop UTC tag (MSBs)</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">Trigger address register</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">Gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">Offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">Reserved register</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">Reserved register</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">Reserved register</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">Sample rate</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">Pre-trigger samples</a></span><br/>
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">Post-trigger samples</a></span><br/>
......@@ -187,13 +187,13 @@ SHOTS
REG
</td>
<td >
<A href="#TRIG_UTC_L">Trigger UTC tag (LSBs)</a>
<A href="#TRIG_POS">Trigger address register</a>
</td>
<td class="td_code">
fmc_adc_core_trig_utc_l
fmc_adc_core_trig_pos
</td>
<td class="td_code">
TRIG_UTC_L
TRIG_POS
</td>
</tr>
<tr class="tr_even">
......@@ -204,13 +204,13 @@ TRIG_UTC_L
REG
</td>
<td >
<A href="#TRIG_UTC_H">Trigger UTC tag (MSBs)</a>
<A href="#GAIN_CAL">Gain calibration register</a>
</td>
<td class="td_code">
fmc_adc_core_trig_utc_h
fmc_adc_core_gain_cal
</td>
<td class="td_code">
TRIG_UTC_H
GAIN_CAL
</td>
</tr>
<tr class="tr_odd">
......@@ -221,13 +221,13 @@ TRIG_UTC_H
REG
</td>
<td >
<A href="#START_UTC_L">Start UTC tag (LSBs)</a>
<A href="#OFFSET_CAL">Offset calibration register</a>
</td>
<td class="td_code">
fmc_adc_core_start_utc_l
fmc_adc_core_offset_cal
</td>
<td class="td_code">
START_UTC_L
OFFSET_CAL
</td>
</tr>
<tr class="tr_even">
......@@ -238,13 +238,13 @@ START_UTC_L
REG
</td>
<td >
<A href="#START_UTC_H">Start UTC tag (MSBs)</a>
<A href="#RESERVED_0">Reserved register</a>
</td>
<td class="td_code">
fmc_adc_core_start_utc_h
fmc_adc_core_reserved_0
</td>
<td class="td_code">
START_UTC_H
RESERVED_0
</td>
</tr>
<tr class="tr_odd">
......@@ -255,13 +255,13 @@ START_UTC_H
REG
</td>
<td >
<A href="#STOP_UTC_L">Stop UTC tag (LSBs)</a>
<A href="#RESERVED_1">Reserved register</a>
</td>
<td class="td_code">
fmc_adc_core_stop_utc_l
fmc_adc_core_reserved_1
</td>
<td class="td_code">
STOP_UTC_L
RESERVED_1
</td>
</tr>
<tr class="tr_even">
......@@ -272,13 +272,13 @@ STOP_UTC_L
REG
</td>
<td >
<A href="#STOP_UTC_H">Stop UTC tag (MSBs)</a>
<A href="#RESERVED_2">Reserved register</a>
</td>
<td class="td_code">
fmc_adc_core_stop_utc_h
fmc_adc_core_reserved_2
</td>
<td class="td_code">
STOP_UTC_H
RESERVED_2
</td>
</tr>
<tr class="tr_odd">
......@@ -357,13 +357,13 @@ SAMP_CNT
REG
</td>
<td >
<A href="#CH1_SSR">Solid state relays control for channel 1</a>
<A href="#CH1">Solid state relays control for channel 1</a>
</td>
<td class="td_code">
fmc_adc_core_ch1_ssr
fmc_adc_core_ch1
</td>
<td class="td_code">
CH1_SSR
CH1
</td>
</tr>
<tr class="tr_even">
......@@ -374,13 +374,13 @@ CH1_SSR
REG
</td>
<td >
<A href="#CH1_VAL">Channel 1 current value</a>
<A href="#CH1">Channel 1 current value</a>
</td>
<td class="td_code">
fmc_adc_core_ch1_val
fmc_adc_core_ch1
</td>
<td class="td_code">
CH1_VAL
CH1
</td>
</tr>
<tr class="tr_odd">
......@@ -391,13 +391,13 @@ CH1_VAL
REG
</td>
<td >
<A href="#CH2_SSR">Solid state relays control for channel 2</a>
<A href="#CH2">Solid state relays control for channel 2</a>
</td>
<td class="td_code">
fmc_adc_core_ch2_ssr
fmc_adc_core_ch2
</td>
<td class="td_code">
CH2_SSR
CH2
</td>
</tr>
<tr class="tr_even">
......@@ -408,13 +408,13 @@ CH2_SSR
REG
</td>
<td >
<A href="#CH2_VAL">Channel 2 current value</a>
<A href="#CH2">Channel 2 current value</a>
</td>
<td class="td_code">
fmc_adc_core_ch2_val
fmc_adc_core_ch2
</td>
<td class="td_code">
CH2_VAL
CH2
</td>
</tr>
<tr class="tr_odd">
......@@ -425,13 +425,13 @@ CH2_VAL
REG
</td>
<td >
<A href="#CH3_SSR">Solid state relays control for channel 3</a>
<A href="#CH3">Solid state relays control for channel 3</a>
</td>
<td class="td_code">
fmc_adc_core_ch3_ssr
fmc_adc_core_ch3
</td>
<td class="td_code">
CH3_SSR
CH3
</td>
</tr>
<tr class="tr_even">
......@@ -442,13 +442,13 @@ CH3_SSR
REG
</td>
<td >
<A href="#CH3_VAL">Channel 3 current value</a>
<A href="#CH3">Channel 3 current value</a>
</td>
<td class="td_code">
fmc_adc_core_ch3_val
fmc_adc_core_ch3
</td>
<td class="td_code">
CH3_VAL
CH3
</td>
</tr>
<tr class="tr_odd">
......@@ -459,13 +459,13 @@ CH3_VAL
REG
</td>
<td >
<A href="#CH4_SSR">Solid state relays control for channel 4</a>
<A href="#CH4">Solid state relays control for channel 4</a>
</td>
<td class="td_code">
fmc_adc_core_ch4_ssr
fmc_adc_core_ch4
</td>
<td class="td_code">
CH4_SSR
CH4
</td>
</tr>
<tr class="tr_even">
......@@ -476,13 +476,13 @@ CH4_SSR
REG
</td>
<td >
<A href="#CH4_VAL">Channel 4 current value</a>
<A href="#CH4">Channel 4 current value</a>
</td>
<td class="td_code">
fmc_adc_core_ch4_val
fmc_adc_core_ch4
</td>
<td class="td_code">
CH4_VAL
CH4
</td>
</tr>
</table>
......@@ -650,6 +650,23 @@ fmc_adc_core_ctl_acq_led_o
wb_ack_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ctl_reserved_o[23:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
fs_clk_i
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
......@@ -661,10 +678,10 @@ wb_ack_o
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
fs_clk_i
</td>
<td class="td_sym_center">
......@@ -733,6 +750,23 @@ fmc_adc_core_sta_serdes_synced_i
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_sta_reserved_i[26:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -857,7 +891,7 @@ fmc_adc_core_trig_cfg_int_trig_sel_o[1:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_trig_cfg_dummy_o[9:0]
fmc_adc_core_trig_cfg_reserved_o[9:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1056,6 +1090,23 @@ fmc_adc_core_shots_nb_o[15:0]
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_shots_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -1078,7 +1129,7 @@ fmc_adc_core_shots_nb_o[15:0]
</td>
<td class="td_pblock_right">
<b>Trigger UTC tag (LSBs):</b>
<b>Trigger address register:</b>
</td>
<td class="td_arrow_right">
......@@ -1095,7 +1146,7 @@ fmc_adc_core_shots_nb_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_trig_utc_l_i[31:0]
fmc_adc_core_trig_pos_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1129,7 +1180,7 @@ fmc_adc_core_trig_utc_l_i[31:0]
</td>
<td class="td_pblock_right">
<b>Trigger UTC tag (MSBs):</b>
<b>Gain calibration register:</b>
</td>
<td class="td_arrow_right">
......@@ -1146,10 +1197,10 @@ fmc_adc_core_trig_utc_l_i[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_trig_utc_h_i[31:0]
fmc_adc_core_gain_cal_o[31:0]
</td>
<td class="td_arrow_right">
&lArr;
&rArr;
</td>
</tr>
<tr>
......@@ -1180,7 +1231,7 @@ fmc_adc_core_trig_utc_h_i[31:0]
</td>
<td class="td_pblock_right">
<b>Start UTC tag (LSBs):</b>
<b>Offset calibration register:</b>
</td>
<td class="td_arrow_right">
......@@ -1197,10 +1248,10 @@ fmc_adc_core_trig_utc_h_i[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_start_utc_l_i[31:0]
fmc_adc_core_offset_cal_o[31:0]
</td>
<td class="td_arrow_right">
&lArr;
&rArr;
</td>
</tr>
<tr>
......@@ -1231,7 +1282,7 @@ fmc_adc_core_start_utc_l_i[31:0]
</td>
<td class="td_pblock_right">
<b>Start UTC tag (MSBs):</b>
<b>Reserved register:</b>
</td>
<td class="td_arrow_right">
......@@ -1248,7 +1299,7 @@ fmc_adc_core_start_utc_l_i[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_start_utc_h_i[31:0]
fmc_adc_core_reserved_0_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1282,7 +1333,7 @@ fmc_adc_core_start_utc_h_i[31:0]
</td>
<td class="td_pblock_right">
<b>Stop UTC tag (LSBs):</b>
<b>Reserved register:</b>
</td>
<td class="td_arrow_right">
......@@ -1299,7 +1350,7 @@ fmc_adc_core_start_utc_h_i[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_stop_utc_l_i[31:0]
fmc_adc_core_reserved_1_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1333,7 +1384,7 @@ fmc_adc_core_stop_utc_l_i[31:0]
</td>
<td class="td_pblock_right">
<b>Stop UTC tag (MSBs):</b>
<b>Reserved register:</b>
</td>
<td class="td_arrow_right">
......@@ -1350,7 +1401,7 @@ fmc_adc_core_stop_utc_l_i[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_stop_utc_h_i[31:0]
fmc_adc_core_reserved_2_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1413,6 +1464,23 @@ fmc_adc_core_sr_deci_o[15:0]
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_sr_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -1617,6 +1685,23 @@ fmc_adc_core_ch1_ssr_o[6:0]
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_reserved_o[24:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -1668,6 +1753,23 @@ fmc_adc_core_ch1_val_i[15:0]
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_reserved_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -1719,6 +1821,23 @@ fmc_adc_core_ch2_ssr_o[6:0]
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_reserved_o[24:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -1770,6 +1889,23 @@ fmc_adc_core_ch2_val_i[15:0]
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_reserved_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -1821,6 +1957,23 @@ fmc_adc_core_ch3_ssr_o[6:0]
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_reserved_o[24:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -1872,6 +2025,23 @@ fmc_adc_core_ch3_val_i[15:0]
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_reserved_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -1923,6 +2093,23 @@ fmc_adc_core_ch4_ssr_o[6:0]
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_reserved_o[24:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -1968,6 +2155,23 @@ fmc_adc_core_ch4_val_i[15:0]
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_reserved_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
......@@ -2035,29 +2239,29 @@ CTL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[23:16]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -2089,29 +2293,29 @@ CTL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -2143,29 +2347,29 @@ CTL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -2249,6 +2453,10 @@ TRIG_LED
ACQ_LED
</b>[<i>read/write</i>]: Manual ACQ LED
<br>Manual control of the front panel ACQ LED
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="STA"></a>
<h3><a name="sect_3_2">3.2. Status register</a></h3>
......@@ -2314,29 +2522,29 @@ STA
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[26:19]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -2368,29 +2576,29 @@ STA
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[18:11]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -2422,29 +2630,29 @@ STA
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[10:3]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -2476,14 +2684,8 @@ STA
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=3 class="td_field">
RESERVED[2:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SERDES_SYNCED
......@@ -2499,6 +2701,12 @@ FSM[2:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
......@@ -2514,6 +2722,10 @@ SERDES_PLL
SERDES_SYNCED
</b>[<i>read-only</i>]: SerDes synchronization status
<br>0: bitslip in progress<br>1: serdes synchronized
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="TRIG_CFG"></a>
<h3><a name="sect_3_3">3.3. Trigger configuration</a></h3>
......@@ -2688,7 +2900,7 @@ INT_TRIG_THRES[7:0]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DUMMY[9:2]
RESERVED[9:2]
</td>
<td >
......@@ -2742,7 +2954,7 @@ DUMMY[9:2]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=2 class="td_field">
DUMMY[1:0]
RESERVED[1:0]
</td>
<td style="border: solid 1px black;" colspan=2 class="td_field">
INT_TRIG_SEL[1:0]
......@@ -2789,8 +3001,8 @@ INT_TRIG_SEL
</b>[<i>read/write</i>]: Channel selection for internal trigger
<br>00: channel 1<br>01: channel 2<br>10: channel 3<br>11: channel 4
<li><b>
DUMMY
</b>[<i>read/write</i>]: Dummy
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
<li><b>
INT_TRIG_THRES
......@@ -3379,29 +3591,29 @@ SHOTS
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -3433,29 +3645,29 @@ SHOTS
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -3572,16 +3784,20 @@ NB[7:0]
NB
</b>[<i>read/write</i>]: Number of shots
<br>Number of shots required in multi-shot mode, set to one for single-shot mode
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="TRIG_UTC_L"></a>
<h3><a name="sect_3_7">3.7. Trigger UTC tag (LSBs)</a></h3>
<a name="TRIG_POS"></a>
<h3><a name="sect_3_7">3.7. Trigger address register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_trig_utc_l
fmc_adc_core_trig_pos
</td>
</tr>
<tr>
......@@ -3597,7 +3813,7 @@ fmc_adc_core_trig_utc_l
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_UTC_L
TRIG_POS
</td>
</tr>
<tr>
......@@ -3638,7 +3854,7 @@ TRIG_UTC_L
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_UTC_L[31:24]
TRIG_POS[31:24]
</td>
<td >
......@@ -3692,7 +3908,7 @@ TRIG_UTC_L[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_UTC_L[23:16]
TRIG_POS[23:16]
</td>
<td >
......@@ -3746,7 +3962,7 @@ TRIG_UTC_L[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_UTC_L[15:8]
TRIG_POS[15:8]
</td>
<td >
......@@ -3800,7 +4016,7 @@ TRIG_UTC_L[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_UTC_L[7:0]
TRIG_POS[7:0]
</td>
<td >
......@@ -3827,19 +4043,19 @@ TRIG_UTC_L[7:0]
</table>
<ul>
<li><b>
TRIG_UTC_L
</b>[<i>read-only</i>]: Trigger UTC tag (LSBs)
<br>UTC time tag (LSBs) of the last trigger, inlcuding the trigger delay
TRIG_POS
</b>[<i>read-only</i>]: Trigger address
<br>Trigger address in DDR memory.<br>Only used in single-shot mode
</ul>
<a name="TRIG_UTC_H"></a>
<h3><a name="sect_3_8">3.8. Trigger UTC tag (MSBs)</a></h3>
<a name="GAIN_CAL"></a>
<h3><a name="sect_3_8">3.8. Gain calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_trig_utc_h
fmc_adc_core_gain_cal
</td>
</tr>
<tr>
......@@ -3855,7 +4071,7 @@ fmc_adc_core_trig_utc_h
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_UTC_H
GAIN_CAL
</td>
</tr>
<tr>
......@@ -3896,7 +4112,7 @@ TRIG_UTC_H
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_UTC_H[31:24]
GAIN_CAL[31:24]
</td>
<td >
......@@ -3950,7 +4166,7 @@ TRIG_UTC_H[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_UTC_H[23:16]
GAIN_CAL[23:16]
</td>
<td >
......@@ -4004,7 +4220,7 @@ TRIG_UTC_H[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_UTC_H[15:8]
GAIN_CAL[15:8]
</td>
<td >
......@@ -4058,7 +4274,7 @@ TRIG_UTC_H[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_UTC_H[7:0]
GAIN_CAL[7:0]
</td>
<td >
......@@ -4085,19 +4301,19 @@ TRIG_UTC_H[7:0]
</table>
<ul>
<li><b>
TRIG_UTC_H
</b>[<i>read-only</i>]: Trigger UTC tag (MSBs)
<br>UTC time tag (MSBs) of the last trigger, inlcuding the trigger delay
GAIN_CAL
</b>[<i>read/write</i>]: Gain calibration
<br>Gain applied to all data coming from the ADC.
</ul>
<a name="START_UTC_L"></a>
<h3><a name="sect_3_9">3.9. Start UTC tag (LSBs)</a></h3>
<a name="OFFSET_CAL"></a>
<h3><a name="sect_3_9">3.9. Offset calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_start_utc_l
fmc_adc_core_offset_cal
</td>
</tr>
<tr>
......@@ -4113,7 +4329,7 @@ fmc_adc_core_start_utc_l
<b>C prefix: </b>
</td>
<td class="td_code">
START_UTC_L
OFFSET_CAL
</td>
</tr>
<tr>
......@@ -4154,7 +4370,7 @@ START_UTC_L
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
START_UTC_L[31:24]
OFFSET_CAL[31:24]
</td>
<td >
......@@ -4208,7 +4424,7 @@ START_UTC_L[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
START_UTC_L[23:16]
OFFSET_CAL[23:16]
</td>
<td >
......@@ -4262,7 +4478,7 @@ START_UTC_L[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
START_UTC_L[15:8]
OFFSET_CAL[15:8]
</td>
<td >
......@@ -4316,7 +4532,7 @@ START_UTC_L[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
START_UTC_L[7:0]
OFFSET_CAL[7:0]
</td>
<td >
......@@ -4343,19 +4559,19 @@ START_UTC_L[7:0]
</table>
<ul>
<li><b>
START_UTC_L
</b>[<i>read-only</i>]: Start UTC tag (LSBs)
<br>UTC time tag (LSBs) of the last start
OFFSET_CAL
</b>[<i>read/write</i>]: Offset calibration
<br>Offset applied to all data coming from the ADC.
</ul>
<a name="START_UTC_H"></a>
<h3><a name="sect_3_10">3.10. Start UTC tag (MSBs)</a></h3>
<a name="RESERVED_0"></a>
<h3><a name="sect_3_10">3.10. Reserved register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_start_utc_h
fmc_adc_core_reserved_0
</td>
</tr>
<tr>
......@@ -4371,7 +4587,7 @@ fmc_adc_core_start_utc_h
<b>C prefix: </b>
</td>
<td class="td_code">
START_UTC_H
RESERVED_0
</td>
</tr>
<tr>
......@@ -4412,7 +4628,7 @@ START_UTC_H
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
START_UTC_H[31:24]
RESERVED_0[31:24]
</td>
<td >
......@@ -4466,7 +4682,7 @@ START_UTC_H[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
START_UTC_H[23:16]
RESERVED_0[23:16]
</td>
<td >
......@@ -4520,7 +4736,7 @@ START_UTC_H[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
START_UTC_H[15:8]
RESERVED_0[15:8]
</td>
<td >
......@@ -4574,7 +4790,7 @@ START_UTC_H[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
START_UTC_H[7:0]
RESERVED_0[7:0]
</td>
<td >
......@@ -4601,19 +4817,19 @@ START_UTC_H[7:0]
</table>
<ul>
<li><b>
START_UTC_H
</b>[<i>read-only</i>]: Start UTC tag (MSBs)
<br>UTC time tag (MSBs) of the last start
RESERVED_0
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="STOP_UTC_L"></a>
<h3><a name="sect_3_11">3.11. Stop UTC tag (LSBs)</a></h3>
<a name="RESERVED_1"></a>
<h3><a name="sect_3_11">3.11. Reserved register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_stop_utc_l
fmc_adc_core_reserved_1
</td>
</tr>
<tr>
......@@ -4629,7 +4845,7 @@ fmc_adc_core_stop_utc_l
<b>C prefix: </b>
</td>
<td class="td_code">
STOP_UTC_L
RESERVED_1
</td>
</tr>
<tr>
......@@ -4670,7 +4886,7 @@ STOP_UTC_L
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
STOP_UTC_L[31:24]
RESERVED_1[31:24]
</td>
<td >
......@@ -4724,7 +4940,7 @@ STOP_UTC_L[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
STOP_UTC_L[23:16]
RESERVED_1[23:16]
</td>
<td >
......@@ -4778,7 +4994,7 @@ STOP_UTC_L[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
STOP_UTC_L[15:8]
RESERVED_1[15:8]
</td>
<td >
......@@ -4832,7 +5048,7 @@ STOP_UTC_L[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
STOP_UTC_L[7:0]
RESERVED_1[7:0]
</td>
<td >
......@@ -4859,19 +5075,19 @@ STOP_UTC_L[7:0]
</table>
<ul>
<li><b>
STOP_UTC_L
</b>[<i>read-only</i>]: Stop UTC tag (LSBs)
<br>UTC time tag (LSBs) of the last stop
RESERVED_1
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="STOP_UTC_H"></a>
<h3><a name="sect_3_12">3.12. Stop UTC tag (MSBs)</a></h3>
<a name="RESERVED_2"></a>
<h3><a name="sect_3_12">3.12. Reserved register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_stop_utc_h
fmc_adc_core_reserved_2
</td>
</tr>
<tr>
......@@ -4887,7 +5103,7 @@ fmc_adc_core_stop_utc_h
<b>C prefix: </b>
</td>
<td class="td_code">
STOP_UTC_H
RESERVED_2
</td>
</tr>
<tr>
......@@ -4928,7 +5144,7 @@ STOP_UTC_H
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
STOP_UTC_H[31:24]
RESERVED_2[31:24]
</td>
<td >
......@@ -4982,7 +5198,7 @@ STOP_UTC_H[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
STOP_UTC_H[23:16]
RESERVED_2[23:16]
</td>
<td >
......@@ -5036,7 +5252,7 @@ STOP_UTC_H[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
STOP_UTC_H[15:8]
RESERVED_2[15:8]
</td>
<td >
......@@ -5090,7 +5306,7 @@ STOP_UTC_H[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
STOP_UTC_H[7:0]
RESERVED_2[7:0]
</td>
<td >
......@@ -5117,9 +5333,9 @@ STOP_UTC_H[7:0]
</table>
<ul>
<li><b>
STOP_UTC_H
</b>[<i>read-only</i>]: Stop UTC tag (MSBs)
<br>UTC time tag (MSBs) of the last stop
RESERVED_2
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="SR"></a>
<h3><a name="sect_3_13">3.13. Sample rate</a></h3>
......@@ -5185,29 +5401,29 @@ SR
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -5239,29 +5455,29 @@ SR
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -5378,6 +5594,10 @@ DECI[7:0]
DECI
</b>[<i>read/write</i>]: Sample rate decimation
<br>Decimation factor
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="PRE_SAMPLES"></a>
<h3><a name="sect_3_14">3.14. Pre-trigger samples</a></h3>
......@@ -6153,7 +6373,7 @@ SAMP_CNT
</b>[<i>read-only</i>]: Sample counter
<br>Counts the number of sample.<br> It is reset on START and then counts the number of pre-trigger + post-trigger samples
</ul>
<a name="CH1_SSR"></a>
<a name="CH1"></a>
<h3><a name="sect_3_17">3.17. Solid state relays control for channel 1</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -6161,7 +6381,7 @@ SAMP_CNT
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch1_ssr
fmc_adc_core_ch1
</td>
</tr>
<tr>
......@@ -6177,7 +6397,7 @@ fmc_adc_core_ch1_ssr
<b>C prefix: </b>
</td>
<td class="td_code">
CH1_SSR
CH1
</td>
</tr>
<tr>
......@@ -6217,29 +6437,29 @@ CH1_SSR
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[24:17]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -6271,29 +6491,29 @@ CH1_SSR
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[16:9]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -6325,29 +6545,29 @@ CH1_SSR
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[8:1]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -6379,11 +6599,11 @@ CH1_SSR
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
CH1_SSR[6:0]
SSR[6:0]
</td>
<td >
......@@ -6407,11 +6627,15 @@ CH1_SSR[6:0]
</table>
<ul>
<li><b>
CH1_SSR
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 1
<br>Controls input voltage range, termination and DC offset error calibration
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH1_VAL"></a>
<a name="CH1"></a>
<h3><a name="sect_3_18">3.18. Channel 1 current value</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -6419,7 +6643,7 @@ CH1_SSR
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch1_val
fmc_adc_core_ch1
</td>
</tr>
<tr>
......@@ -6435,7 +6659,7 @@ fmc_adc_core_ch1_val
<b>C prefix: </b>
</td>
<td class="td_code">
CH1_VAL
CH1
</td>
</tr>
<tr>
......@@ -6475,29 +6699,29 @@ CH1_VAL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -6529,29 +6753,29 @@ CH1_VAL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -6584,7 +6808,7 @@ CH1_VAL
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH1_VAL[15:8]
VAL[15:8]
</td>
<td >
......@@ -6638,7 +6862,7 @@ CH1_VAL[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH1_VAL[7:0]
VAL[7:0]
</td>
<td >
......@@ -6665,11 +6889,15 @@ CH1_VAL[7:0]
</table>
<ul>
<li><b>
CH1_VAL
VAL
</b>[<i>read-only</i>]: Channel 1 current value
<br>Current ADC raw value
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH2_SSR"></a>
<a name="CH2"></a>
<h3><a name="sect_3_19">3.19. Solid state relays control for channel 2</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -6677,7 +6905,7 @@ CH1_VAL
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch2_ssr
fmc_adc_core_ch2
</td>
</tr>
<tr>
......@@ -6693,7 +6921,7 @@ fmc_adc_core_ch2_ssr
<b>C prefix: </b>
</td>
<td class="td_code">
CH2_SSR
CH2
</td>
</tr>
<tr>
......@@ -6733,29 +6961,29 @@ CH2_SSR
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[24:17]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -6787,29 +7015,29 @@ CH2_SSR
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[16:9]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -6841,29 +7069,29 @@ CH2_SSR
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[8:1]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -6895,11 +7123,11 @@ CH2_SSR
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
CH2_SSR[6:0]
SSR[6:0]
</td>
<td >
......@@ -6923,11 +7151,15 @@ CH2_SSR[6:0]
</table>
<ul>
<li><b>
CH2_SSR
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 2
<br>Controls input voltage range, termination and DC offset error calibration
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH2_VAL"></a>
<a name="CH2"></a>
<h3><a name="sect_3_20">3.20. Channel 2 current value</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -6935,7 +7167,7 @@ CH2_SSR
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch2_val
fmc_adc_core_ch2
</td>
</tr>
<tr>
......@@ -6951,7 +7183,7 @@ fmc_adc_core_ch2_val
<b>C prefix: </b>
</td>
<td class="td_code">
CH2_VAL
CH2
</td>
</tr>
<tr>
......@@ -6991,29 +7223,29 @@ CH2_VAL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -7045,29 +7277,29 @@ CH2_VAL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -7100,7 +7332,7 @@ CH2_VAL
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH2_VAL[15:8]
VAL[15:8]
</td>
<td >
......@@ -7154,7 +7386,7 @@ CH2_VAL[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH2_VAL[7:0]
VAL[7:0]
</td>
<td >
......@@ -7181,11 +7413,15 @@ CH2_VAL[7:0]
</table>
<ul>
<li><b>
CH2_VAL
VAL
</b>[<i>read-only</i>]: Channel 2 current value
<br>Current ADC raw value
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH3_SSR"></a>
<a name="CH3"></a>
<h3><a name="sect_3_21">3.21. Solid state relays control for channel 3</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -7193,7 +7429,7 @@ CH2_VAL
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch3_ssr
fmc_adc_core_ch3
</td>
</tr>
<tr>
......@@ -7209,7 +7445,7 @@ fmc_adc_core_ch3_ssr
<b>C prefix: </b>
</td>
<td class="td_code">
CH3_SSR
CH3
</td>
</tr>
<tr>
......@@ -7249,29 +7485,29 @@ CH3_SSR
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[24:17]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -7303,29 +7539,29 @@ CH3_SSR
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[16:9]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -7357,29 +7593,29 @@ CH3_SSR
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[8:1]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -7411,11 +7647,11 @@ CH3_SSR
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
CH3_SSR[6:0]
SSR[6:0]
</td>
<td >
......@@ -7439,11 +7675,15 @@ CH3_SSR[6:0]
</table>
<ul>
<li><b>
CH3_SSR
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 3
<br>Controls input voltage range, termination and DC offset error calibration
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH3_VAL"></a>
<a name="CH3"></a>
<h3><a name="sect_3_22">3.22. Channel 3 current value</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -7451,7 +7691,7 @@ CH3_SSR
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch3_val
fmc_adc_core_ch3
</td>
</tr>
<tr>
......@@ -7467,7 +7707,7 @@ fmc_adc_core_ch3_val
<b>C prefix: </b>
</td>
<td class="td_code">
CH3_VAL
CH3
</td>
</tr>
<tr>
......@@ -7507,29 +7747,29 @@ CH3_VAL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -7561,29 +7801,29 @@ CH3_VAL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -7616,7 +7856,7 @@ CH3_VAL
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH3_VAL[15:8]
VAL[15:8]
</td>
<td >
......@@ -7670,7 +7910,7 @@ CH3_VAL[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH3_VAL[7:0]
VAL[7:0]
</td>
<td >
......@@ -7697,11 +7937,15 @@ CH3_VAL[7:0]
</table>
<ul>
<li><b>
CH3_VAL
VAL
</b>[<i>read-only</i>]: Channel 3 current value
<br>Current ADC raw value
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH4_SSR"></a>
<a name="CH4"></a>
<h3><a name="sect_3_23">3.23. Solid state relays control for channel 4</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -7709,7 +7953,7 @@ CH3_VAL
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch4_ssr
fmc_adc_core_ch4
</td>
</tr>
<tr>
......@@ -7725,7 +7969,7 @@ fmc_adc_core_ch4_ssr
<b>C prefix: </b>
</td>
<td class="td_code">
CH4_SSR
CH4
</td>
</tr>
<tr>
......@@ -7765,29 +8009,29 @@ CH4_SSR
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[24:17]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -7819,29 +8063,29 @@ CH4_SSR
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[16:9]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -7873,29 +8117,29 @@ CH4_SSR
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[8:1]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -7927,11 +8171,11 @@ CH4_SSR
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
CH4_SSR[6:0]
SSR[6:0]
</td>
<td >
......@@ -7955,11 +8199,15 @@ CH4_SSR[6:0]
</table>
<ul>
<li><b>
CH4_SSR
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 4
<br>Controls input voltage range, termination and DC offset error calibration
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH4_VAL"></a>
<a name="CH4"></a>
<h3><a name="sect_3_24">3.24. Channel 4 current value</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -7967,7 +8215,7 @@ CH4_SSR
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch4_val
fmc_adc_core_ch4
</td>
</tr>
<tr>
......@@ -7983,7 +8231,7 @@ fmc_adc_core_ch4_val
<b>C prefix: </b>
</td>
<td class="td_code">
CH4_VAL
CH4
</td>
</tr>
<tr>
......@@ -8023,29 +8271,29 @@ CH4_VAL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -8077,29 +8325,29 @@ CH4_VAL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -8132,7 +8380,7 @@ CH4_VAL
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH4_VAL[15:8]
VAL[15:8]
</td>
<td >
......@@ -8186,7 +8434,7 @@ CH4_VAL[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH4_VAL[7:0]
VAL[7:0]
</td>
<td >
......@@ -8213,9 +8461,13 @@ CH4_VAL[7:0]
</table>
<ul>
<li><b>
CH4_VAL
VAL
</b>[<i>read-only</i>]: Channel 4 current value
<br>Current ADC raw value
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
View file @ e7e2f3c9
......@@ -68,6 +68,16 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 24;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
......@@ -100,6 +110,16 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 27;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
......@@ -158,9 +178,9 @@ peripheral {
};
field {
name = "Dummy";
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "dummy";
prefix = "reserved";
type = SLV;
size = 10;
access_bus = READ_WRITE;
......@@ -219,15 +239,25 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Trigger UTC tag (LSBs)";
prefix = "trig_utc_l";
name = "Trigger address register";
prefix = "trig_pos";
field {
name = "Trigger UTC tag (LSBs)";
description = "UTC time tag (LSBs) of the last trigger, inlcuding the trigger delay";
name = "Trigger address";
description = "Trigger address in DDR memory.\nOnly used in single-shot mode";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -236,40 +266,40 @@ peripheral {
};
reg {
name = "Trigger UTC tag (MSBs)";
prefix = "trig_utc_h";
name = "Gain calibration register";
prefix = "gain_cal";
field {
name = "Trigger UTC tag (MSBs)";
description = "UTC time tag (MSBs) of the last trigger, inlcuding the trigger delay";
name = "Gain calibration";
description = "Gain applied to all data coming from the ADC.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Start UTC tag (LSBs)";
prefix = "start_utc_l";
name = "Offset calibration register";
prefix = "offset_cal";
field {
name = "Start UTC tag (LSBs)";
description = "UTC time tag (LSBs) of the last start";
name = "Offset calibration";
description = "Offset applied to all data coming from the ADC.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Start UTC tag (MSBs)";
prefix = "start_utc_h";
name = "Reserved register";
prefix = "reserved_0";
field {
name = "Start UTC tag (MSBs)";
description = "UTC time tag (MSBs) of the last start";
name = "Reserved";
description = "Ignore on read, write with 0's";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -278,12 +308,12 @@ peripheral {
};
reg {
name = "Stop UTC tag (LSBs)";
prefix = "stop_utc_l";
name = "Reserved register";
prefix = "reserved_1";
field {
name = "Stop UTC tag (LSBs)";
description = "UTC time tag (LSBs) of the last stop";
name = "Reserved";
description = "Ignore on read, write with 0's";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -292,12 +322,12 @@ peripheral {
};
reg {
name = "Stop UTC tag (MSBs)";
prefix = "stop_utc_h";
name = "Reserved register";
prefix = "reserved_2";
field {
name = "Stop UTC tag (MSBs)";
description = "UTC time tag (MSBs) of the last stop";
name = "Reserved";
description = "Ignore on read, write with 0's";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -319,6 +349,16 @@ peripheral {
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
......@@ -365,118 +405,206 @@ peripheral {
reg {
name = "Solid state relays control for channel 1";
prefix = "ch1_ssr";
prefix = "ch1";
field {
name = "Solid state relays control for channel 1";
description = "Controls input voltage range, termination and DC offset error calibration";
prefix = "ssr";
type = SLV;
size = 7;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 25;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 1 current value";
prefix = "ch1_val";
prefix = "ch1";
field {
name = "Channel 1 current value";
description = "Current ADC raw value";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Solid state relays control for channel 2";
prefix = "ch2_ssr";
prefix = "ch2";
field {
name = "Solid state relays control for channel 2";
description = "Controls input voltage range, termination and DC offset error calibration";
prefix = "ssr";
type = SLV;
size = 7;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 25;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 2 current value";
prefix = "ch2_val";
prefix = "ch2";
field {
name = "Channel 2 current value";
description = "Current ADC raw value";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Solid state relays control for channel 3";
prefix = "ch3_ssr";
prefix = "ch3";
field {
name = "Solid state relays control for channel 3";
description = "Controls input voltage range, termination and DC offset error calibration";
prefix = "ssr";
type = SLV;
size = 7;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 25;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 3 current value";
prefix = "ch3_val";
prefix = "ch3";
field {
name = "Channel 3 current value";
description = "Current ADC raw value";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Solid state relays control for channel 4";
prefix = "ch4_ssr";
prefix = "ch4";
field {
name = "Solid state relays control for channel 4";
description = "Controls input voltage range, termination and DC offset error calibration";
prefix = "ssr";
type = SLV;
size = 7;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 25;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 4 current value";
prefix = "ch4_val";
prefix = "ch4";
field {
name = "Channel 4 current value";
description = "Current ADC raw value";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
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