This document describes the hdl developed to support the FmcAdc100m14b4cha@footnote{http://www.ohwr.org/projects/fmc-adc-100m14b4cha} mezzanine card on the SPEC@footnote{http://www.ohwr.org/projects/spec} carrier card.
This chapter describes each internal block of the FPGA.
All blocks (except the memory controller) are connected to the PCIe bridge interface through a wishbone bus. The DDR memory can only be access through DMA.
The figure @ref{fig:firmware_arch} illustrates the FPGA architecture. The peripherals connected to each block are also shown.
A crossbar from the general-cores@footnote{http://www.ohwr.org/projects/general-cores} library is used to map the Wishbone slaves in the BAR 0 address space.
The Wishbone crossbar also implements SDB@footnote{http://www.ohwr.org/projects/fpga-config-space} records. Those records describes the Wishbone slaves and their mapping on the bus.
Note that some of the cores from the general-cores library are based on cores from OpenCores@footnote{http://opencores.org/}. Therefore, the documentation for those cores is hosted on the OpenCores website.
The register description for the cores from the carrier control and status, the time-tagging core, the interrupt controller and the ADC core can be found in annexe.
This block is the interface between the GN4124@footnote{PCI Express bridge from Semtech (was Gennum)} local bus and the other blocks in the FPGA.
The GN4124 is a four lane PCI Express bridge. In addition to th PHY, it also contains the data link and transaction layers.
The GN4124 bridge is used to access the FPGA registers, but also to generate MSI interrupts and re-program the FPGA.
The BAR 4 (Base Address Register) allows access to the GN4124 internal registers.
The BAR 0 is connected to the local bus and therefore allows access to the FPGA.
The GN4124 core is made of a local bus interface with the GN4124 chip, a Wishbone bus master mapped to BAR0 and a DMA controller. The DMA controller has two Wishbone ports. A Wishbone slave to configure the DMA controller and a Wishbone master to access the DDR memory.
- wb addr alignment
- ddr memory access (interleaved, no address converter)
This block contains control and status registers related to the carrier board.
A first register allows to readout the carrier PCB revision and carrier type.
Another register signals the presence of a mezzanine in the FMC slot, gives the status of the local bus and system PLLs and indicates the DDR memory controller calibration state.
The last register of this block allows to control the carrier's LEDs on the front panel. There is on red and one green LED.
The carrier SPI master is not implemented. It is meant to control DACs connected to VCXO for White Rabbit@footnote{http://www.ohwr.org/projects/white-rabbit} applications.
The interrupt controller has four interrupt inputs and one interrupt request output.
It also have one interrupt enable mask register and one interrupt source register.
Each time a valid rising edge is detected on one of the inputs, a pulse is generated on the interrupt request output.
A rising edge is valid if the corresponding bit in the interrupt enable mask register is set.
When a valid rising edge is detected, the corresponding bit in the interrupt source register is set as well. This indicates to the host which source caused the interrput.
To clear a bit in the interrupt source register, a '1' must be written to it.
- TODO explain the multi-irq register (or remove it!)
The following equation shows the relation between the input voltage and the offset (applied by the DAC). Note that the offset from the DAC is subtracted from the input voltage.
The following equation shows the relation between the input voltage and the offset (applied by the DAC).
Note that the offset from the DAC is subtracted from the input voltage.
@code{Vout = Vin - Vdac}
...
...
@@ -329,6 +486,19 @@ The first column "Byte offset" represents the offset within the binary file.
