Commit d27e5a09 authored by Matthieu Cattin's avatar Matthieu Cattin

doc, hdl: add note about the sampling frequency.

The sampling frequency can't be changed dynamically in the current design.
This is due to the internal fpga pll that is configured for a fixed 400MHz input.
parent 70a2a755
......@@ -583,6 +583,8 @@ Then the data clock (DCO) output of the LTC2174 is connected to the FPGA.
The data clock is four times the sampling clock.
The sampling clock (@code{fs_clk}) and the ADC data de-serialiser clock (@code{serdes_clk}) are derived from the data clock using a PLL (internal to the FPGA).
@b{Note:} The internal PLL expects a 400MHz input frequency (define in the hdl code), therefore the sampling frequency has to be 100MHz and can't be change dynamically.
@c TODO : possibility to control the Si570 via I2C
The ADC core implements a sampling clock frequency meter.
......@@ -1222,6 +1224,7 @@ The @ref{fig:mem_multi_shot} shows the shots organisation in the DDR memory.
@c DONE @item Add hysteresis on internal trigger slope detection (-> non-monotonic signals, noisy).
@c DONE @item Add debug mode: ch1=analog input, ch2=int_trig_over_thres, ch3=int_trig, ch4=trig
@c DONE @item Make data saturation programmable.
@item Trigger hold-off in multi-shot mode?
@end itemize
......
......@@ -524,6 +524,8 @@ begin
-- Clock PLL for SerDes
-- LTC2174-14 must be configured in 16-bit serialization
-- dco_clk = 4*fs_clk = 400MHz
-- WARNING : The PLL expects a 400MHz input frequency, therefore the sampling
-- frequency has to be 100MHz and can't be change dynamically.
------------------------------------------------------------------------------
cmp_serdes_clk_pll : PLL_BASE
generic map (
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment