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FMC ADC 100M 14b 4cha - Gateware
Commit d1834cdc authored by Dimitris Lampridis's avatar Dimitris Lampridis
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migrate SVEC REF CSR to Cheby

parent 440df6d9
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doc/manual/svec_carrier_csr.html 0 → 100644
View file @ d1834cdc
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hdl/syn/svec_ref_design_wr/svec_ref_fmc_adc_100Ms_wr.ucf
View file @ d1834cdc
......@@ -367,8 +367,8 @@ NET "fp_led_column_o[*]" IOSTANDARD="LVCMOS33";
#----------------------------------------
NET "fp_gpio1_o" LOC = T28;
NET "fp_gpio2_o" LOC = R30;
NET "fp_gpio3_i" LOC = V27;
NET "fp_gpio4_i" LOC = U29;
NET "fp_gpio3_o" LOC = V27;
NET "fp_gpio4_o" LOC = U29;
NET "fp_gpio1_a2b_o" LOC = T30;
NET "fp_gpio2_a2b_o" LOC = R29;
NET "fp_gpio34_a2b_o" LOC = V28;
......
hdl/testbench/include/svec_carrier_csr.v 0 → 100644
View file @ d1834cdc
`define SVEC_CARRIER_CSR_SIZE 16
`define ADDR_SVEC_CARRIER_CSR_CARRIER 'h0
`define SVEC_CARRIER_CSR_CARRIER_PCB_REV_OFFSET 0
`define SVEC_CARRIER_CSR_CARRIER_PCB_REV 'h1f
`define SVEC_CARRIER_CSR_CARRIER_RESERVED_OFFSET 5
`define SVEC_CARRIER_CSR_CARRIER_RESERVED 'hffe0
`define SVEC_CARRIER_CSR_CARRIER_TYPE_OFFSET 16
`define SVEC_CARRIER_CSR_CARRIER_TYPE 'hffff0000
`define ADDR_SVEC_CARRIER_CSR_STAT 'h4
`define SVEC_CARRIER_CSR_STAT_FMC0_PRES_OFFSET 0
`define SVEC_CARRIER_CSR_STAT_FMC0_PRES 'h1
`define SVEC_CARRIER_CSR_STAT_FMC1_PRES_OFFSET 1
`define SVEC_CARRIER_CSR_STAT_FMC1_PRES 'h2
`define SVEC_CARRIER_CSR_STAT_SYS_PLL_LCK_OFFSET 2
`define SVEC_CARRIER_CSR_STAT_SYS_PLL_LCK 'h4
`define SVEC_CARRIER_CSR_STAT_DDR0_CAL_DONE_OFFSET 3
`define SVEC_CARRIER_CSR_STAT_DDR0_CAL_DONE 'h8
`define SVEC_CARRIER_CSR_STAT_DDR1_CAL_DONE_OFFSET 4
`define SVEC_CARRIER_CSR_STAT_DDR1_CAL_DONE 'h10
`define ADDR_SVEC_CARRIER_CSR_CTRL 'h8
`define SVEC_CARRIER_CSR_CTRL_FP_LEDS_MAN_OFFSET 0
`define SVEC_CARRIER_CSR_CTRL_FP_LEDS_MAN 'hffff
`define ADDR_SVEC_CARRIER_CSR_RST 'hc
`define SVEC_CARRIER_CSR_RST_FMC0_OFFSET 0
`define SVEC_CARRIER_CSR_RST_FMC0 'h1
`define SVEC_CARRIER_CSR_RST_FMC1_OFFSET 1
`define SVEC_CARRIER_CSR_RST_FMC1 'h2
hdl/top/svec_ref_design/Makefile 0 → 100644
View file @ d1834cdc
SIM =../../testbench/include
DOC =../../../doc/manual
SW =../../../software/include/hw
SOURCES = $(wildcard *.cheby)
TARGETS = $(SOURCES:.cheby=.vhd)
all: $(TARGETS)
.PHONY: $(TARGETS)
$(TARGETS): %.vhd : %.cheby
@echo "\n\033[34m\033[1m-> Processing file $<\033[0m"
@cheby -i $< --gen-hdl=$@
@cheby -i $< \
--gen-doc=$(DOC)/$(@:.vhd=.html) \
--gen-consts=$(SIM)/$(@:.vhd=.v) \
--gen-c=$(SW)/$(@:.vhd=.h)
hdl/top/svec_ref_design/Manifest.py
View file @ d1834cdc
files = [
"svec_ref_fmc_adc_100Ms.vhd",
"carrier_csr.vhd",
"carrier_csr_wbgen2_pkg.vhd",
"svec_carrier_csr.vhd",
]
modules = {
......
hdl/top/svec_ref_design/carrier_csr.vhd deleted 100644 → 0
View file @ 440df6d9
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for SVEC carrier control and status registers
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Fri Feb 23 15:39:10 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.carrier_csr_wbgen2_pkg.all;
entity carrier_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_carrier_csr_in_registers;
regs_o : out t_carrier_csr_out_registers
);
end carrier_csr;
architecture syn of carrier_csr is
signal carrier_csr_ctrl_fp_leds_man_int : std_logic_vector(15 downto 0);
signal carrier_csr_rst_fmc0_int : std_logic ;
signal carrier_csr_rst_fmc1_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
begin
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
carrier_csr_ctrl_fp_leds_man_int <= "0000000000000000";
carrier_csr_rst_fmc0_int <= '0';
carrier_csr_rst_fmc1_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
end if;
rddata_reg(4 downto 0) <= regs_i.carrier_pcb_rev_i;
rddata_reg(15 downto 5) <= regs_i.carrier_reserved_i;
rddata_reg(31 downto 16) <= regs_i.carrier_type_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.stat_fmc0_pres_i;
rddata_reg(1) <= regs_i.stat_fmc1_pres_i;
rddata_reg(2) <= regs_i.stat_sys_pll_lck_i;
rddata_reg(3) <= regs_i.stat_ddr0_cal_done_i;
rddata_reg(4) <= regs_i.stat_ddr1_cal_done_i;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
carrier_csr_ctrl_fp_leds_man_int <= wrdata_reg(15 downto 0);
end if;
rddata_reg(15 downto 0) <= carrier_csr_ctrl_fp_leds_man_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
carrier_csr_rst_fmc0_int <= wrdata_reg(0);
carrier_csr_rst_fmc1_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= carrier_csr_rst_fmc0_int;
rddata_reg(1) <= carrier_csr_rst_fmc1_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- PCB revision
-- Reserved register
-- Carrier type
-- FMC 1 presence
-- FMC 2 presence
-- System clock PLL status
-- DDR3 bank 4 calibration status
-- DDR3 bank 5 calibration status
-- Front panel LED manual control
regs_o.ctrl_fp_leds_man_o <= carrier_csr_ctrl_fp_leds_man_int;
-- State of the FMC 1 reset line
regs_o.rst_fmc0_o <= carrier_csr_rst_fmc0_int;
-- State of the FMC 2 reset line
regs_o.rst_fmc1_o <= carrier_csr_rst_fmc1_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/top/svec_ref_design/carrier_csr_wbgen2_pkg.vhd deleted 100644 → 0
View file @ 440df6d9
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for SVEC carrier control and status registers
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Fri Feb 23 15:39:10 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package carrier_csr_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_carrier_csr_in_registers is record
carrier_pcb_rev_i : std_logic_vector(4 downto 0);
carrier_reserved_i : std_logic_vector(10 downto 0);
carrier_type_i : std_logic_vector(15 downto 0);
stat_fmc0_pres_i : std_logic;
stat_fmc1_pres_i : std_logic;
stat_sys_pll_lck_i : std_logic;
stat_ddr0_cal_done_i : std_logic;
stat_ddr1_cal_done_i : std_logic;
end record;
constant c_carrier_csr_in_registers_init_value: t_carrier_csr_in_registers := (
carrier_pcb_rev_i => (others => '0'),
carrier_reserved_i => (others => '0'),
carrier_type_i => (others => '0'),
stat_fmc0_pres_i => '0',
stat_fmc1_pres_i => '0',
stat_sys_pll_lck_i => '0',
stat_ddr0_cal_done_i => '0',
stat_ddr1_cal_done_i => '0'
);
-- Output registers (WB slave -> user design)
type t_carrier_csr_out_registers is record
ctrl_fp_leds_man_o : std_logic_vector(15 downto 0);
rst_fmc0_o : std_logic;
rst_fmc1_o : std_logic;
end record;
constant c_carrier_csr_out_registers_init_value: t_carrier_csr_out_registers := (
ctrl_fp_leds_man_o => (others => '0'),
rst_fmc0_o => '0',
rst_fmc1_o => '0'
);
function "or" (left, right: t_carrier_csr_in_registers) return t_carrier_csr_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body carrier_csr_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if x(i) = '1' then
tmp(i):= '1';
else
tmp(i):= '0';
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_carrier_csr_in_registers) return t_carrier_csr_in_registers is
variable tmp: t_carrier_csr_in_registers;
begin
tmp.carrier_pcb_rev_i := f_x_to_zero(left.carrier_pcb_rev_i) or f_x_to_zero(right.carrier_pcb_rev_i);
tmp.carrier_reserved_i := f_x_to_zero(left.carrier_reserved_i) or f_x_to_zero(right.carrier_reserved_i);
tmp.carrier_type_i := f_x_to_zero(left.carrier_type_i) or f_x_to_zero(right.carrier_type_i);
tmp.stat_fmc0_pres_i := f_x_to_zero(left.stat_fmc0_pres_i) or f_x_to_zero(right.stat_fmc0_pres_i);
tmp.stat_fmc1_pres_i := f_x_to_zero(left.stat_fmc1_pres_i) or f_x_to_zero(right.stat_fmc1_pres_i);
tmp.stat_sys_pll_lck_i := f_x_to_zero(left.stat_sys_pll_lck_i) or f_x_to_zero(right.stat_sys_pll_lck_i);
tmp.stat_ddr0_cal_done_i := f_x_to_zero(left.stat_ddr0_cal_done_i) or f_x_to_zero(right.stat_ddr0_cal_done_i);
tmp.stat_ddr1_cal_done_i := f_x_to_zero(left.stat_ddr1_cal_done_i) or f_x_to_zero(right.stat_ddr1_cal_done_i);
return tmp;
end function;
end package body;
hdl/top/svec_ref_design/svec_carrier_csr.cheby 0 → 100644
View file @ d1834cdc
memory-map:
bus: wb-32-be
name: svec_carrier_csr
description: SVEC carrier control and status registers
comment: |
Wishbone slave for control and status registers related to the SVEC FMC carrier
x-hdl:
busgroup: True
iogroup: carrier_csr
children:
- reg:
name: carrier
address: 0x00000000
width: 32
access: ro
description: Carrier type and PCB version
children:
- field:
name: pcb_rev
range: 4-0
description: PCB revision
comment: |
Binary coded PCB layout revision.
- field:
name: reserved
range: 15-5
description: Reserved register
comment: |
Ignore on read, write with 0's.
- field:
name: type
range: 31-16
description: Carrier type
comment: |
Carrier type identifier
1 = SPEC
2 = SVEC
3 = VFC
4 = SPEXI
- reg:
name: stat
address: 0x00000004
width: 32
access: ro
description: Status
children:
- field:
name: fmc0_pres
range: 0
description: FMC 1 presence
comment: |
0: FMC slot 1 is populated
1: FMC slot 1 is not populated.
- field:
name: fmc1_pres
range: 1
description: FMC 2 presence
comment: |
0: FMC slot 2 is populated
1: FMC slot 2 is not populated.
- field:
name: sys_pll_lck
range: 2
description: System clock PLL status
comment: |
0: not locked
1: locked.
- field:
name: ddr0_cal_done
range: 3
description: DDR3 bank 4 calibration status
comment: |
0: not done
1: done.
- field:
name: ddr1_cal_done
range: 4
description: DDR3 bank 5 calibration status
comment: |
0: not done
1: done.
- reg:
name: ctrl
address: 0x00000008
width: 32
access: rw
description: Control
children:
- field:
name: fp_leds_man
range: 15-0
description: Front panel LED manual control
comment: |
Height front panel LED, two bits per LED.
00 = OFF
01 = Green
10 = Red
11 = Orange
- reg:
name: rst
address: 0x0000000c
width: 32
access: wo
description: Reset Register
comment: |
Controls software reset of the mezzanines including the ddr interface and the time-tagging core.
children:
- field:
name: fmc0
range: 0
description: State of the FMC 1 reset line
comment: |
write 0: Normal FMC operation
write 1: FMC is held in reset
- field:
name: fmc1
range: 1
description: State of the FMC 2 reset line
comment: |
write 0: Normal FMC operation
write 1: FMC is held in reset
hdl/top/svec_ref_design/svec_carrier_csr.vhd 0 → 100644
View file @ d1834cdc
-- Do not edit; this file was generated by Cheby using these options:
-- -i svec_carrier_csr.cheby --gen-hdl=svec_carrier_csr.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package svec_carrier_csr_pkg is
type t_carrier_csr_master_out is record
ctrl_fp_leds_man : std_logic_vector(15 downto 0);
rst_fmc0 : std_logic;
rst_fmc1 : std_logic;
end record t_carrier_csr_master_out;
subtype t_carrier_csr_slave_in is t_carrier_csr_master_out;
type t_carrier_csr_slave_out is record
carrier_pcb_rev : std_logic_vector(4 downto 0);
carrier_reserved : std_logic_vector(10 downto 0);
carrier_type : std_logic_vector(15 downto 0);
stat_fmc0_pres : std_logic;
stat_fmc1_pres : std_logic;
stat_sys_pll_lck : std_logic;
stat_ddr0_cal_done : std_logic;
stat_ddr1_cal_done : std_logic;
end record t_carrier_csr_slave_out;
subtype t_carrier_csr_master_in is t_carrier_csr_slave_out;
end svec_carrier_csr_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.svec_carrier_csr_pkg.all;
entity svec_carrier_csr is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- Wires and registers
carrier_csr_i : in t_carrier_csr_master_in;
carrier_csr_o : out t_carrier_csr_master_out
);
end svec_carrier_csr;
architecture syn of svec_carrier_csr is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal ctrl_fp_leds_man_reg : std_logic_vector(15 downto 0);
signal rst_fmc0_reg : std_logic;
signal rst_fmc1_reg : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
begin
-- WB decode signals
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- Assign outputs
carrier_csr_o.ctrl_fp_leds_man <= ctrl_fp_leds_man_reg;
carrier_csr_o.rst_fmc0 <= rst_fmc0_reg;
carrier_csr_o.rst_fmc1 <= rst_fmc1_reg;
-- Process for write requests.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
ctrl_fp_leds_man_reg <= "0000000000000000";
rst_fmc0_reg <= '0';
rst_fmc1_reg <= '0';
else
wr_ack_int <= '0';
case wb_i.adr(3 downto 2) is
when "00" =>
-- Register carrier
when "01" =>
-- Register stat
when "10" =>
-- Register ctrl
if wr_int = '1' then
ctrl_fp_leds_man_reg <= wb_i.dat(15 downto 0);
end if;
wr_ack_int <= wr_int;
when "11" =>
-- Register rst
if wr_int = '1' then
rst_fmc0_reg <= wb_i.dat(0);
rst_fmc1_reg <= wb_i.dat(1);
end if;
wr_ack_int <= wr_int;
when others =>
wr_ack_int <= wr_int;
end case;
end if;
end if;
end process;
-- Process for registers read.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack1_int <= '0';
else
reg_rdat_int <= (others => '0');
case wb_i.adr(3 downto 2) is
when "00" =>
-- carrier
reg_rdat_int(4 downto 0) <= carrier_csr_i.carrier_pcb_rev;
reg_rdat_int(15 downto 5) <= carrier_csr_i.carrier_reserved;
reg_rdat_int(31 downto 16) <= carrier_csr_i.carrier_type;
rd_ack1_int <= rd_int;
when "01" =>
-- stat
reg_rdat_int(0) <= carrier_csr_i.stat_fmc0_pres;
reg_rdat_int(1) <= carrier_csr_i.stat_fmc1_pres;
reg_rdat_int(2) <= carrier_csr_i.stat_sys_pll_lck;
reg_rdat_int(3) <= carrier_csr_i.stat_ddr0_cal_done;
reg_rdat_int(4) <= carrier_csr_i.stat_ddr1_cal_done;
rd_ack1_int <= rd_int;
when "10" =>
-- ctrl
reg_rdat_int(15 downto 0) <= ctrl_fp_leds_man_reg;
rd_ack1_int <= rd_int;
when "11" =>
-- rst
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
end if;
end if;
end process;
-- Process for read requests.
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
case wb_i.adr(3 downto 2) is
when "00" =>
-- carrier
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "01" =>
-- stat
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "10" =>
-- ctrl
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "11" =>
-- rst
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
end process;
end syn;
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @ d1834cdc
......@@ -41,7 +41,7 @@ use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.fmc_adc_mezzanine_pkg.all;
use work.synthesis_descriptor.all;
use work.carrier_csr_wbgen2_pkg.all;
use work.svec_carrier_csr_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_svec_pkg.all;
......@@ -475,8 +475,8 @@ architecture rtl of svec_ref_fmc_adc_100Ms is
signal tm_time_valid : std_logic;
-- IO for CSR registers
signal csr_regin : t_carrier_csr_in_registers;
signal csr_regout : t_carrier_csr_out_registers;
signal csr_regin : t_carrier_csr_master_in;
signal csr_regout : t_carrier_csr_master_out;
begin
......@@ -677,39 +677,27 @@ begin
-- Carrier status (PLL, FMC presence)
-- Front panel LED manual control
------------------------------------------------------------------------------
cmp_carrier_csr : entity work.carrier_csr
cmp_carrier_csr : entity work.svec_carrier_csr
port map (
rst_n_i => rst_sys_62m5_n,
clk_sys_i => clk_sys_62m5,
wb_adr_i => cnx_slave_in(c_WB_SLAVE_SVEC_CSR).adr(3 downto 2),
wb_dat_i => cnx_slave_in(c_WB_SLAVE_SVEC_CSR).dat,
wb_dat_o => cnx_slave_out(c_WB_SLAVE_SVEC_CSR).dat,
wb_cyc_i => cnx_slave_in(c_WB_SLAVE_SVEC_CSR).cyc,
wb_sel_i => cnx_slave_in(c_WB_SLAVE_SVEC_CSR).sel,
wb_stb_i => cnx_slave_in(c_WB_SLAVE_SVEC_CSR).stb,
wb_we_i => cnx_slave_in(c_WB_SLAVE_SVEC_CSR).we,
wb_ack_o => cnx_slave_out(c_WB_SLAVE_SVEC_CSR).ack,
wb_stall_o => open,
regs_i => csr_regin,
regs_o => csr_regout);
csr_regin.carrier_pcb_rev_i <= pcbrev_i;
csr_regin.carrier_reserved_i <= (others => '0');
csr_regin.carrier_type_i <= c_CARRIER_TYPE;
csr_regin.stat_fmc0_pres_i <= fmc_prsnt_m2c_n_i(0);
csr_regin.stat_fmc1_pres_i <= fmc_prsnt_m2c_n_i(1);
csr_regin.stat_sys_pll_lck_i <= sys_clk_pll_locked;
csr_regin.stat_ddr0_cal_done_i <= ddr_calib_done(0);
csr_regin.stat_ddr1_cal_done_i <= ddr_calib_done(1);
led_state_csr <= csr_regout.ctrl_fp_leds_man_o;
sw_rst_fmc(0) <= csr_regout.rst_fmc0_o;
sw_rst_fmc(1) <= csr_regout.rst_fmc1_o;
-- Unused wishbone signals
cnx_slave_out(c_WB_SLAVE_SVEC_CSR).err <= '0';
cnx_slave_out(c_WB_SLAVE_SVEC_CSR).rty <= '0';
cnx_slave_out(c_WB_SLAVE_SVEC_CSR).stall <= '0';
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
wb_i => cnx_slave_in(c_WB_SLAVE_SVEC_CSR),
wb_o => cnx_slave_out(c_WB_SLAVE_SVEC_CSR),
carrier_csr_i => csr_regin,
carrier_csr_o => csr_regout);
csr_regin.carrier_pcb_rev <= pcbrev_i;
csr_regin.carrier_reserved <= (others => '0');
csr_regin.carrier_type <= c_CARRIER_TYPE;
csr_regin.stat_fmc0_pres <= fmc_prsnt_m2c_n_i(0);
csr_regin.stat_fmc1_pres <= fmc_prsnt_m2c_n_i(1);
csr_regin.stat_sys_pll_lck <= sys_clk_pll_locked;
csr_regin.stat_ddr0_cal_done <= ddr_calib_done(0);
csr_regin.stat_ddr1_cal_done <= ddr_calib_done(1);
led_state_csr <= csr_regout.ctrl_fp_leds_man;
sw_rst_fmc(0) <= csr_regout.rst_fmc0;
sw_rst_fmc(1) <= csr_regout.rst_fmc1;
------------------------------------------------------------------------------
-- Vectored interrupt controller (VIC)
......
hdl/top/svec_ref_design/wb_gen/Makefile deleted 100644 → 0
View file @ 440df6d9
WBGEN2=$(shell which wbgen2)
RTL=../
TEX=../../../../doc/manual/svec/
carrier_csr:
$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_wbgen2_pkg.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
hdl/top/svec_ref_design/wb_gen/carrier_csr.h deleted 100644 → 0
View file @ 440df6d9
/*
Register definitions for slave core: SVEC carrier control and status registers
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Fri Feb 23 15:39:10 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_CARRIER_CSR_WB
#define __WBGEN2_REGDEFS_CARRIER_CSR_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Carrier type and PCB version */
/* definitions for field: PCB revision in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_PCB_REV_MASK WBGEN2_GEN_MASK(0, 5)
#define CARRIER_CSR_CARRIER_PCB_REV_SHIFT 0
#define CARRIER_CSR_CARRIER_PCB_REV_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define CARRIER_CSR_CARRIER_PCB_REV_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Reserved register in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_RESERVED_MASK WBGEN2_GEN_MASK(5, 11)
#define CARRIER_CSR_CARRIER_RESERVED_SHIFT 5
#define CARRIER_CSR_CARRIER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 11)
#define CARRIER_CSR_CARRIER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 5, 11)
/* definitions for field: Carrier type in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_TYPE_MASK WBGEN2_GEN_MASK(16, 16)
#define CARRIER_CSR_CARRIER_TYPE_SHIFT 16
#define CARRIER_CSR_CARRIER_TYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define CARRIER_CSR_CARRIER_TYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Status */
/* definitions for field: FMC 1 presence in reg: Status */
#define CARRIER_CSR_STAT_FMC0_PRES WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC 2 presence in reg: Status */
#define CARRIER_CSR_STAT_FMC1_PRES WBGEN2_GEN_MASK(1, 1)
/* definitions for field: System clock PLL status in reg: Status */
#define CARRIER_CSR_STAT_SYS_PLL_LCK WBGEN2_GEN_MASK(2, 1)
/* definitions for field: DDR3 bank 4 calibration status in reg: Status */
#define CARRIER_CSR_STAT_DDR0_CAL_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for field: DDR3 bank 5 calibration status in reg: Status */
#define CARRIER_CSR_STAT_DDR1_CAL_DONE WBGEN2_GEN_MASK(4, 1)
/* definitions for register: Control */
/* definitions for field: Front panel LED manual control in reg: Control */
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_MASK WBGEN2_GEN_MASK(0, 16)
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_SHIFT 0
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Reset Register */
/* definitions for field: State of the FMC 1 reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC0 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: State of the FMC 2 reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC1 WBGEN2_GEN_MASK(1, 1)
PACKED struct CARRIER_CSR_WB {
/* [0x0]: REG Carrier type and PCB version */
uint32_t CARRIER;
/* [0x4]: REG Status */
uint32_t STAT;
/* [0x8]: REG Control */
uint32_t CTRL;
/* [0xc]: REG Reset Register */
uint32_t RST;
};
#endif
hdl/top/svec_ref_design/wb_gen/carrier_csr.htm deleted 100644 → 0
View file @ 440df6d9
This diff is collapsed.
hdl/top/svec_ref_design/wb_gen/carrier_csr.wb deleted 100644 → 0
View file @ 440df6d9
peripheral {
name = "SVEC carrier control and status registers";
description = "Wishbone slave for control and status registers related to the SVEC FMC carrier";
hdl_entity = "carrier_csr";
prefix = "carrier_csr";
reg {
name = "Carrier type and PCB version";
prefix = "carrier";
field {
name = "PCB revision";
description = "Binary coded PCB layout revision.";
prefix = "pcb_rev";
type = SLV;
size = 5;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Reserved register";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 11;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Carrier type";
description = "Carrier type identifier\n1 = SPEC\n2 = SVEC\n3 = VFC\n4 = SPEXI";
prefix = "type";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Status";
prefix = "stat";
field {
name = "FMC 1 presence";
description = "0: FMC slot 1 is populated\n1: FMC slot 1 is not populated.";
prefix = "fmc0_pres";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "FMC 2 presence";
description = "0: FMC slot 2 is populated\n1: FMC slot 2 is not populated.";
prefix = "fmc1_pres";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "System clock PLL status";
description = "0: not locked\n1: locked.";
prefix = "sys_pll_lck";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "DDR3 bank 4 calibration status";
description = "0: not done\n1: done.";
prefix = "ddr0_cal_done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "DDR3 bank 5 calibration status";
description = "0: not done\n1: done.";
prefix = "ddr1_cal_done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Control";
prefix = "ctrl";
field {
name = "Front panel LED manual control";
description = "Height front panel LED, two bits per LED.\n00 = OFF\n01 = Green\n10 = Red\n11 = Orange";
prefix = "fp_leds_man";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Reset Register";
prefix = "rst";
description = "Controls software reset of the mezzanines including the ddr interface and the time-tagging core.";
field {
name = "State of the FMC 1 reset line";
description = "write 0: Normal FMC operation\
write 1: FMC is held in reset";
type = BIT;
size = 1;
prefix = "fmc0";
access_bus = WRITE;
access_dev = READ;
};
field {
name = "State of the FMC 2 reset line";
description = "write 0: Normal FMC operation\
write 1: FMC is held in reset";
type = BIT;
size = 1;
prefix = "fmc1";
access_bus = WRITE;
access_dev = READ;
};
};
};
software/include/hw/svec_carrier_csr.h 0 → 100644
View file @ d1834cdc
#ifndef __CHEBY__SVEC_CARRIER_CSR__H__
#define __CHEBY__SVEC_CARRIER_CSR__H__
#define SVEC_CARRIER_CSR_SIZE 16
/* Carrier type and PCB version */
#define SVEC_CARRIER_CSR_CARRIER 0x0UL
#define SVEC_CARRIER_CSR_CARRIER_PCB_REV_MASK 0x1fUL
#define SVEC_CARRIER_CSR_CARRIER_PCB_REV_SHIFT 0
#define SVEC_CARRIER_CSR_CARRIER_RESERVED_MASK 0xffe0UL
#define SVEC_CARRIER_CSR_CARRIER_RESERVED_SHIFT 5
#define SVEC_CARRIER_CSR_CARRIER_TYPE_MASK 0xffff0000UL
#define SVEC_CARRIER_CSR_CARRIER_TYPE_SHIFT 16
/* Status */
#define SVEC_CARRIER_CSR_STAT 0x4UL
#define SVEC_CARRIER_CSR_STAT_FMC0_PRES 0x1UL
#define SVEC_CARRIER_CSR_STAT_FMC1_PRES 0x2UL
#define SVEC_CARRIER_CSR_STAT_SYS_PLL_LCK 0x4UL
#define SVEC_CARRIER_CSR_STAT_DDR0_CAL_DONE 0x8UL
#define SVEC_CARRIER_CSR_STAT_DDR1_CAL_DONE 0x10UL
/* Control */
#define SVEC_CARRIER_CSR_CTRL 0x8UL
#define SVEC_CARRIER_CSR_CTRL_FP_LEDS_MAN_MASK 0xffffUL
#define SVEC_CARRIER_CSR_CTRL_FP_LEDS_MAN_SHIFT 0
/* Reset Register */
#define SVEC_CARRIER_CSR_RST 0xcUL
#define SVEC_CARRIER_CSR_RST_FMC0 0x1UL
#define SVEC_CARRIER_CSR_RST_FMC1 0x2UL
struct svec_carrier_csr {
/* [0x0]: REG (ro) Carrier type and PCB version */
uint32_t carrier;
/* [0x4]: REG (ro) Status */
uint32_t stat;
/* [0x8]: REG (rw) Control */
uint32_t ctrl;
/* [0xc]: REG (wo) Reset Register */
uint32_t rst;
};
#endif /* __CHEBY__SVEC_CARRIER_CSR__H__ */
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