sim: fix fmc_adc_mezzanine simulation

d1059605 · Dimitris Lampridis · c70ccee6 · d1059605 · d1059605
Commit d1059605 authored Nov 27, 2018 by Dimitris Lampridis
Hide whitespace changes
Inline Side-by-side

Showing with 5 additions and 4 deletions

Manifest.py hdl/testbench/fmc_adc_mezzanine/Manifest.py +1 -3

main.sv hdl/testbench/fmc_adc_mezzanine/main.sv +4 -1

No files found.
--- a/hdl/testbench/fmc_adc_mezzanine/Manifest.py
+++ b/hdl/testbench/fmc_adc_mezzanine/Manifest.py
@@ -12,7 +12,7 @@ fetchto = "../../ip_cores"
 include_dirs = [
    "../include",
    fetchto + "/general-cores/sim/",
-    fetchto + "/general-cores/modules/wishbone/wb_spi/"
+    fetchto + "/general-cores/modules/wishbone/wb_spi/",
 ]

 files = [
@@ -27,5 +27,3 @@ modules = {
        "git://ohwr.org/hdl-core-lib/general-cores.git",
    ],
 }
-
-ctrls = [ "bank3_64b_32b" ]
--- a/hdl/testbench/fmc_adc_mezzanine/main.sv
+++ b/hdl/testbench/fmc_adc_mezzanine/main.sv
@@ -53,6 +53,7 @@ module main;
 	      .trig_irq_o          (),
 	      .acq_end_irq_o       (),
 	      .eic_irq_o           (),
+	      .acq_cfg_ok_o        (),
 	      .ext_trigger_p_i     (ext_trig),
 	      .ext_trigger_n_i     (~ext_trig),
 	      .adc_dco_p_i         (adc0_dco),
@@ -156,13 +157,15 @@ module main;

   initial begin

-      CBusAccessor acc;
+      CWishboneAccessor acc;
      uint64_t val, expected;

      $timeformat (-6, 3, "us", 10);

      acc = Host.get_accessor();

+      acc.set_mode(PIPELINED);
+
      #1us;

      expected = 'h5344422d;