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FMC ADC 100M 14b 4cha - Gateware
Commit cdfee3dd authored by mcattin's avatar mcattin
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Replace empty bits in registers by reserved. 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@93 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent e7e2f3c9
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Showing with 242 additions and 213 deletions
hdl/spec/rtl/carrier_csr.vhd
View file @ cdfee3dd
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Tue Aug 30 10:54:01 2011
-- Created : Wed Nov 23 09:30:44 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -28,8 +28,8 @@ entity carrier_csr is
wb_ack_o : out std_logic;
-- Port for std_logic_vector field: 'PCB revision' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Dummy' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_dummy_i : in std_logic_vector(11 downto 0);
-- Port for std_logic_vector field: 'Reserved register' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_reserved_i : in std_logic_vector(11 downto 0);
-- Port for std_logic_vector field: 'Carrier type' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_type_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Bitstream type' in reg: 'Bitstream type'
......@@ -44,12 +44,16 @@ entity carrier_csr is
carrier_csr_stat_sys_pll_lck_i : in std_logic;
-- Port for BIT field: 'DDR3 calibration status' in reg: 'Status'
carrier_csr_stat_ddr3_cal_done_i : in std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Status'
carrier_csr_stat_reserved_i : in std_logic_vector(27 downto 0);
-- Port for BIT field: 'Green LED' in reg: 'Control'
carrier_csr_ctrl_led_green_o : out std_logic;
-- Port for BIT field: 'Red LED' in reg: 'Control'
carrier_csr_ctrl_led_red_o : out std_logic;
-- Port for BIT field: 'DAC clear' in reg: 'Control'
carrier_csr_ctrl_dac_clr_n_o : out std_logic
carrier_csr_ctrl_dac_clr_n_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Control'
carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0)
);
end carrier_csr;
......@@ -58,6 +62,7 @@ architecture syn of carrier_csr is
signal carrier_csr_ctrl_led_green_int : std_logic ;
signal carrier_csr_ctrl_led_red_int : std_logic ;
signal carrier_csr_ctrl_dac_clr_n_int : std_logic ;
signal carrier_csr_ctrl_reserved_int : std_logic_vector(28 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -90,6 +95,7 @@ begin
carrier_csr_ctrl_led_green_int <= '0';
carrier_csr_ctrl_led_red_int <= '0';
carrier_csr_ctrl_dac_clr_n_int <= '0';
carrier_csr_ctrl_reserved_int <= "00000000000000000000000000000";
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -106,7 +112,7 @@ begin
if (wb_we_i = '1') then
else
rddata_reg(3 downto 0) <= carrier_csr_carrier_pcb_rev_i;
rddata_reg(15 downto 4) <= carrier_csr_carrier_dummy_i;
rddata_reg(15 downto 4) <= carrier_csr_carrier_reserved_i;
rddata_reg(31 downto 16) <= carrier_csr_carrier_type_i;
end if;
ack_sreg(0) <= '1';
......@@ -132,34 +138,7 @@ begin
rddata_reg(1) <= carrier_csr_stat_p2l_pll_lck_i;
rddata_reg(2) <= carrier_csr_stat_sys_pll_lck_i;
rddata_reg(3) <= carrier_csr_stat_ddr3_cal_done_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(31 downto 4) <= carrier_csr_stat_reserved_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
......@@ -168,39 +147,12 @@ begin
carrier_csr_ctrl_led_green_int <= wrdata_reg(0);
carrier_csr_ctrl_led_red_int <= wrdata_reg(1);
carrier_csr_ctrl_dac_clr_n_int <= wrdata_reg(2);
carrier_csr_ctrl_reserved_int <= wrdata_reg(31 downto 3);
else
rddata_reg(0) <= carrier_csr_ctrl_led_green_int;
rddata_reg(1) <= carrier_csr_ctrl_led_red_int;
rddata_reg(2) <= carrier_csr_ctrl_dac_clr_n_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(31 downto 3) <= carrier_csr_ctrl_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
......@@ -218,7 +170,7 @@ begin
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- PCB revision
-- Dummy
-- Reserved register
-- Carrier type
-- Bitstream type
-- Bitstream date
......@@ -226,12 +178,15 @@ begin
-- GN4142 core P2L PLL status
-- System clock PLL status
-- DDR3 calibration status
-- Reserved
-- Green LED
carrier_csr_ctrl_led_green_o <= carrier_csr_ctrl_led_green_int;
-- Red LED
carrier_csr_ctrl_led_red_o <= carrier_csr_ctrl_led_red_int;
-- DAC clear
carrier_csr_ctrl_dac_clr_n_o <= carrier_csr_ctrl_dac_clr_n_int;
-- Reserved
carrier_csr_ctrl_reserved_o <= carrier_csr_ctrl_reserved_int;
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
......
hdl/spec/wb_gen/carrier_csr.h
View file @ cdfee3dd
......@@ -3,7 +3,7 @@
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Tue Aug 30 10:54:01 2011
* Created : Wed Nov 23 09:30:44 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -39,11 +39,11 @@
#define CARRIER_CSR_CARRIER_PCB_REV_W(value) WBGEN2_GEN_WRITE(value, 0, 4)
#define CARRIER_CSR_CARRIER_PCB_REV_R(reg) WBGEN2_GEN_READ(reg, 0, 4)
/* definitions for field: Dummy in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_DUMMY_MASK WBGEN2_GEN_MASK(4, 12)
#define CARRIER_CSR_CARRIER_DUMMY_SHIFT 4
#define CARRIER_CSR_CARRIER_DUMMY_W(value) WBGEN2_GEN_WRITE(value, 4, 12)
#define CARRIER_CSR_CARRIER_DUMMY_R(reg) WBGEN2_GEN_READ(reg, 4, 12)
/* definitions for field: Reserved register in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_RESERVED_MASK WBGEN2_GEN_MASK(4, 12)
#define CARRIER_CSR_CARRIER_RESERVED_SHIFT 4
#define CARRIER_CSR_CARRIER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 12)
#define CARRIER_CSR_CARRIER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 12)
/* definitions for field: Carrier type in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_TYPE_MASK WBGEN2_GEN_MASK(16, 16)
......@@ -69,6 +69,12 @@
/* definitions for field: DDR3 calibration status in reg: Status */
#define CARRIER_CSR_STAT_DDR3_CAL_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Status */
#define CARRIER_CSR_STAT_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define CARRIER_CSR_STAT_RESERVED_SHIFT 4
#define CARRIER_CSR_STAT_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define CARRIER_CSR_STAT_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Control */
/* definitions for field: Green LED in reg: Control */
......@@ -80,6 +86,12 @@
/* definitions for field: DAC clear in reg: Control */
#define CARRIER_CSR_CTRL_DAC_CLR_N WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reserved in reg: Control */
#define CARRIER_CSR_CTRL_RESERVED_MASK WBGEN2_GEN_MASK(3, 29)
#define CARRIER_CSR_CTRL_RESERVED_SHIFT 3
#define CARRIER_CSR_CTRL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define CARRIER_CSR_CTRL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 29)
PACKED struct CARRIER_CSR_WB {
/* [0x0]: REG Carrier type and PCB version */
uint32_t CARRIER;
......
hdl/spec/wb_gen/carrier_csr.htm
View file @ cdfee3dd
......@@ -192,7 +192,7 @@ wb_addr_i[2:0]
</td>
<td class="td_pblock_right">
carrier_csr_carrier_dummy_i[11:0]
carrier_csr_carrier_reserved_i[11:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -425,6 +425,23 @@ carrier_csr_stat_ddr3_cal_done_i
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_stat_reserved_i[27:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -504,6 +521,23 @@ carrier_csr_ctrl_dac_clr_n_o
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_ctrl_reserved_o[28:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
......@@ -680,7 +714,7 @@ TYPE[7:0]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DUMMY[11:4]
RESERVED[11:4]
</td>
<td >
......@@ -734,7 +768,7 @@ DUMMY[11:4]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=4 class="td_field">
DUMMY[3:0]
RESERVED[3:0]
</td>
<td style="border: solid 1px black;" colspan=4 class="td_field">
PCB_REV[3:0]
......@@ -763,11 +797,11 @@ PCB_REV[3:0]
<li><b>
PCB_REV
</b>[<i>read-only</i>]: PCB revision
<br>Binary coded PCB layout revision
<br>Binary coded PCB layout revision.
<li><b>
DUMMY
</b>[<i>read-only</i>]: Dummy
<br>Ignore on read, write with 0's
RESERVED
</b>[<i>read-only</i>]: Reserved register
<br>Ignore on read, write with 0's.
<li><b>
TYPE
</b>[<i>read-only</i>]: Carrier type
......@@ -1029,7 +1063,7 @@ BITSTREAM_TYPE[7:0]
<li><b>
BITSTREAM_TYPE
</b>[<i>read-only</i>]: Bitstream type
<br>Bitstream (firmware) type, unsigned 32-bit number
<br>Bitstream (firmware) type, unsigned 32-bit number.
</ul>
<a name="BITSTREAM_DATE"></a>
<h3><a name="sect_3_3">3.3. Bitstream date</a></h3>
......@@ -1287,7 +1321,7 @@ BITSTREAM_DATE[7:0]
<li><b>
BITSTREAM_DATE
</b>[<i>read-only</i>]: Bitstream date
<br>Bitstream generation date, unsigned 32-bit UTC time
<br>Bitstream generation date, unsigned 32-bit UTC time.
</ul>
<a name="STAT"></a>
<h3><a name="sect_3_4">3.4. Status</a></h3>
......@@ -1353,29 +1387,29 @@ STAT
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[27:20]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -1407,29 +1441,29 @@ STAT
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[19:12]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -1461,29 +1495,29 @@ STAT
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[11:4]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -1515,17 +1549,8 @@ STAT
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=4 class="td_field">
RESERVED[3:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DDR3_CAL_DONE
......@@ -1538,6 +1563,15 @@ P2L_PLL_LCK
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC_PRES
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
......@@ -1545,19 +1579,23 @@ FMC_PRES
<li><b>
FMC_PRES
</b>[<i>read-only</i>]: FMC presence
<br>0: FMC slot is populated<br>1: FMC slot is not populated
<br>0: FMC slot is populated<br>1: FMC slot is not populated.
<li><b>
P2L_PLL_LCK
</b>[<i>read-only</i>]: GN4142 core P2L PLL status
<br>0: not locked<br>1: locked
<br>0: not locked<br>1: locked.
<li><b>
SYS_PLL_LCK
</b>[<i>read-only</i>]: System clock PLL status
<br>0: not locked<br>1: locked
<br>0: not locked<br>1: locked.
<li><b>
DDR3_CAL_DONE
</b>[<i>read-only</i>]: DDR3 calibration status
<br>0: not done<br>1: done
<br>0: not done<br>1: done.
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's.
</ul>
<a name="CTRL"></a>
<h3><a name="sect_3_5">3.5. Control</a></h3>
......@@ -1623,29 +1661,29 @@ CTRL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[28:21]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -1677,29 +1715,29 @@ CTRL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[20:13]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -1731,29 +1769,29 @@ CTRL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[12:5]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -1785,20 +1823,8 @@ CTRL
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=5 class="td_field">
RESERVED[4:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DAC_CLR_N
......@@ -1808,6 +1834,18 @@ LED_RED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
LED_GREEN
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
......@@ -1824,6 +1862,10 @@ LED_RED
DAC_CLR_N
</b>[<i>read/write</i>]: DAC clear
<br>Active low clear signal for VCXO DACs
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
......
hdl/spec/wb_gen/carrier_csr.wb
View file @ cdfee3dd
......@@ -11,7 +11,7 @@ peripheral {
field {
name = "PCB revision";
description = "Binary coded PCB layout revision";
description = "Binary coded PCB layout revision.";
prefix = "pcb_rev";
type = SLV;
size = 4;
......@@ -20,9 +20,9 @@ peripheral {
};
field {
name = "Dummy";
description = "Ignore on read, write with 0's";
prefix = "dummy";
name = "Reserved register";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 12;
access_bus = READ_ONLY;
......@@ -46,7 +46,7 @@ peripheral {
field {
name = "Bitstream type";
description = "Bitstream (firmware) type, unsigned 32-bit number";
description = "Bitstream (firmware) type, unsigned 32-bit number.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -60,7 +60,7 @@ peripheral {
field {
name = "Bitstream date";
description = "Bitstream generation date, unsigned 32-bit UTC time";
description = "Bitstream generation date, unsigned 32-bit UTC time.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -74,7 +74,7 @@ peripheral {
field {
name = "FMC presence";
description = "0: FMC slot is populated\n1: FMC slot is not populated";
description = "0: FMC slot is populated\n1: FMC slot is not populated.";
prefix = "fmc_pres";
type = BIT;
access_bus = READ_ONLY;
......@@ -83,7 +83,7 @@ peripheral {
field {
name = "GN4142 core P2L PLL status";
description = "0: not locked\n1: locked";
description = "0: not locked\n1: locked.";
prefix = "p2l_pll_lck";
type = BIT;
access_bus = READ_ONLY;
......@@ -92,7 +92,7 @@ peripheral {
field {
name = "System clock PLL status";
description = "0: not locked\n1: locked";
description = "0: not locked\n1: locked.";
prefix = "sys_pll_lck";
type = BIT;
access_bus = READ_ONLY;
......@@ -101,12 +101,22 @@ peripheral {
field {
name = "DDR3 calibration status";
description = "0: not done\n1: done";
description = "0: not done\n1: done.";
prefix = "ddr3_cal_done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
......@@ -139,6 +149,16 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 29;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- ram {
......
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