Commit cbc4c992 authored by mcattin's avatar mcattin

Change offset gain correction block to signed, data from ADC is two's complement.

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@104 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent a7afca0e
files = ["fmc_adc_100Ms_core.vhd",
"fmc_adc_100Ms_csr.vhd",
"offset_gain.vhd"]
"offset_gain_s.vhd"]
......@@ -170,32 +170,32 @@ architecture rtl of fmc_adc_100Ms_core is
fmc_adc_core_ch1_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch1_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch1_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch1_offset_val_o : out std_logic_vector(16 downto 0);
fmc_adc_core_ch1_offset_reserved_o : out std_logic_vector(14 downto 0);
fmc_adc_core_ch1_offset_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch1_offset_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch2_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch2_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch2_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch2_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch2_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch2_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch2_offset_val_o : out std_logic_vector(16 downto 0);
fmc_adc_core_ch2_offset_reserved_o : out std_logic_vector(14 downto 0);
fmc_adc_core_ch2_offset_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch2_offset_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch3_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch3_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch3_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch3_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch3_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch3_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch3_offset_val_o : out std_logic_vector(16 downto 0);
fmc_adc_core_ch3_offset_reserved_o : out std_logic_vector(14 downto 0);
fmc_adc_core_ch3_offset_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch3_offset_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch4_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch4_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch4_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch4_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_offset_val_o : out std_logic_vector(16 downto 0);
fmc_adc_core_ch4_offset_reserved_o : out std_logic_vector(14 downto 0)
fmc_adc_core_ch4_offset_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_offset_reserved_o : out std_logic_vector(15 downto 0)
);
end component fmc_adc_100Ms_csr;
......@@ -218,16 +218,16 @@ architecture rtl of fmc_adc_100Ms_core is
);
end component ext_pulse_sync;
component offset_gain
component offset_gain_s
port (
rst_n_i : in std_logic; --! Reset (active low)
clk_i : in std_logic; --! Clock
offset_i : in std_logic_vector(16 downto 0); --! Signed offset input (two's complement)
offset_i : in std_logic_vector(15 downto 0); --! Signed offset input (two's complement)
gain_i : in std_logic_vector(15 downto 0); --! Unsigned gain input
data_i : in std_logic_vector(15 downto 0); --! Unsigned data input
data_o : out std_logic_vector(15 downto 0) --! Unsigned data output
data_i : in std_logic_vector(15 downto 0); --! Signed data input (two's complement)
data_o : out std_logic_vector(15 downto 0) --! Signed data output (two's complement)
);
end component offset_gain;
end component offset_gain_s;
component adc_sync_fifo
port (
......@@ -366,7 +366,7 @@ architecture rtl of fmc_adc_100Ms_core is
-- Gain/offset calibration
signal gain_calibr : std_logic_vector(63 downto 0);
signal offset_calibr : std_logic_vector(67 downto 0);
signal offset_calibr : std_logic_vector(63 downto 0);
signal data_calibr_in : std_logic_vector(63 downto 0);
signal data_calibr_out : std_logic_vector(63 downto 0);
......@@ -704,7 +704,7 @@ begin
fmc_adc_core_ch1_sta_reserved_i => (others => '0'),
fmc_adc_core_ch1_gain_val_o => gain_calibr(15 downto 0),
fmc_adc_core_ch1_gain_reserved_o => open,
fmc_adc_core_ch1_offset_val_o => offset_calibr(16 downto 0),
fmc_adc_core_ch1_offset_val_o => offset_calibr(15 downto 0),
fmc_adc_core_ch1_offset_reserved_o => open,
fmc_adc_core_ch2_ctl_ssr_o => gpio_ssr_ch2_o,
fmc_adc_core_ch2_ctl_reserved_o => open,
......@@ -712,7 +712,7 @@ begin
fmc_adc_core_ch2_sta_reserved_i => (others => '0'),
fmc_adc_core_ch2_gain_val_o => gain_calibr(31 downto 16),
fmc_adc_core_ch2_gain_reserved_o => open,
fmc_adc_core_ch2_offset_val_o => offset_calibr(33 downto 17),
fmc_adc_core_ch2_offset_val_o => offset_calibr(31 downto 16),
fmc_adc_core_ch2_offset_reserved_o => open,
fmc_adc_core_ch3_ctl_ssr_o => gpio_ssr_ch3_o,
fmc_adc_core_ch3_ctl_reserved_o => open,
......@@ -720,7 +720,7 @@ begin
fmc_adc_core_ch3_sta_reserved_i => (others => '0'),
fmc_adc_core_ch3_gain_val_o => gain_calibr(47 downto 32),
fmc_adc_core_ch3_gain_reserved_o => open,
fmc_adc_core_ch3_offset_val_o => offset_calibr(50 downto 34),
fmc_adc_core_ch3_offset_val_o => offset_calibr(47 downto 32),
fmc_adc_core_ch3_offset_reserved_o => open,
fmc_adc_core_ch4_ctl_ssr_o => gpio_ssr_ch4_o,
fmc_adc_core_ch4_ctl_reserved_o => open,
......@@ -728,7 +728,7 @@ begin
fmc_adc_core_ch4_sta_reserved_i => (others => '0'),
fmc_adc_core_ch4_gain_val_o => gain_calibr(63 downto 48),
fmc_adc_core_ch4_gain_reserved_o => open,
fmc_adc_core_ch4_offset_val_o => offset_calibr(67 downto 51),
fmc_adc_core_ch4_offset_val_o => offset_calibr(63 downto 48),
fmc_adc_core_ch4_offset_reserved_o => open
);
......@@ -879,11 +879,11 @@ begin
-- Offset and gain calibration
------------------------------------------------------------------------------
l_offset_gain_calibr : for I in 0 to 3 generate
cmp_offset_gain_calibr : offset_gain
cmp_offset_gain_calibr : offset_gain_s
port map(
rst_n_i => fs_rst_n,
clk_i => fs_clk,
offset_i => offset_calibr((I+1)*17-1 downto I*17),
offset_i => offset_calibr((I+1)*16-1 downto I*16),
gain_i => gain_calibr((I+1)*16-1 downto I*16),
data_i => data_calibr_in((I+1)*16-1 downto I*16),
data_o => data_calibr_out((I+1)*16-1 downto I*16)
......
This diff is collapsed.
......@@ -173,6 +173,20 @@ begin
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-298, 17));
gain_i <= std_logic_vector(to_unsigned(32090, 16));
data_i <= std_logic_vector(to_unsigned(60857, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 17));
gain_i <= std_logic_vector(to_unsigned(16384, 16));
data_i <= std_logic_vector(to_unsigned(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
-- offset_i <= "010000000000000";
offset_i <= "01111111111111111";
......
......@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Fri Nov 25 16:25:51 2011
* Created : Fri Dec 16 08:44:17 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -200,16 +200,16 @@
/* definitions for register: Channel 1 offset calibration register */
/* definitions for field: Offset calibration for channel 1 in reg: Channel 1 offset calibration register */
#define FMC_ADC_CORE_CH1_OFFSET_VAL_MASK WBGEN2_GEN_MASK(0, 17)
#define FMC_ADC_CORE_CH1_OFFSET_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH1_OFFSET_VAL_SHIFT 0
#define FMC_ADC_CORE_CH1_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 17)
#define FMC_ADC_CORE_CH1_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 17)
#define FMC_ADC_CORE_CH1_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH1_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 1 offset calibration register */
#define FMC_ADC_CORE_CH1_OFFSET_RESERVED_MASK WBGEN2_GEN_MASK(17, 15)
#define FMC_ADC_CORE_CH1_OFFSET_RESERVED_SHIFT 17
#define FMC_ADC_CORE_CH1_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 17, 15)
#define FMC_ADC_CORE_CH1_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 17, 15)
#define FMC_ADC_CORE_CH1_OFFSET_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH1_OFFSET_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH1_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH1_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 2 control register */
......@@ -256,16 +256,16 @@
/* definitions for register: Channel 2 offset calibration register */
/* definitions for field: Offset calibration for channel 2 in reg: Channel 2 offset calibration register */
#define FMC_ADC_CORE_CH2_OFFSET_VAL_MASK WBGEN2_GEN_MASK(0, 17)
#define FMC_ADC_CORE_CH2_OFFSET_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH2_OFFSET_VAL_SHIFT 0
#define FMC_ADC_CORE_CH2_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 17)
#define FMC_ADC_CORE_CH2_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 17)
#define FMC_ADC_CORE_CH2_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH2_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 2 offset calibration register */
#define FMC_ADC_CORE_CH2_OFFSET_RESERVED_MASK WBGEN2_GEN_MASK(17, 15)
#define FMC_ADC_CORE_CH2_OFFSET_RESERVED_SHIFT 17
#define FMC_ADC_CORE_CH2_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 17, 15)
#define FMC_ADC_CORE_CH2_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 17, 15)
#define FMC_ADC_CORE_CH2_OFFSET_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH2_OFFSET_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH2_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH2_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 3 control register */
......@@ -312,16 +312,16 @@
/* definitions for register: Channel 3 offset calibration register */
/* definitions for field: Offset calibration for channel 3 in reg: Channel 3 offset calibration register */
#define FMC_ADC_CORE_CH3_OFFSET_VAL_MASK WBGEN2_GEN_MASK(0, 17)
#define FMC_ADC_CORE_CH3_OFFSET_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH3_OFFSET_VAL_SHIFT 0
#define FMC_ADC_CORE_CH3_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 17)
#define FMC_ADC_CORE_CH3_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 17)
#define FMC_ADC_CORE_CH3_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH3_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 3 offset calibration register */
#define FMC_ADC_CORE_CH3_OFFSET_RESERVED_MASK WBGEN2_GEN_MASK(17, 15)
#define FMC_ADC_CORE_CH3_OFFSET_RESERVED_SHIFT 17
#define FMC_ADC_CORE_CH3_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 17, 15)
#define FMC_ADC_CORE_CH3_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 17, 15)
#define FMC_ADC_CORE_CH3_OFFSET_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH3_OFFSET_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH3_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH3_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 4 control register */
......@@ -368,16 +368,16 @@
/* definitions for register: Channel 4 offset calibration register */
/* definitions for field: Offset calibration for channel 4 in reg: Channel 4 offset calibration register */
#define FMC_ADC_CORE_CH4_OFFSET_VAL_MASK WBGEN2_GEN_MASK(0, 17)
#define FMC_ADC_CORE_CH4_OFFSET_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH4_OFFSET_VAL_SHIFT 0
#define FMC_ADC_CORE_CH4_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 17)
#define FMC_ADC_CORE_CH4_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 17)
#define FMC_ADC_CORE_CH4_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH4_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 4 offset calibration register */
#define FMC_ADC_CORE_CH4_OFFSET_RESERVED_MASK WBGEN2_GEN_MASK(17, 15)
#define FMC_ADC_CORE_CH4_OFFSET_RESERVED_SHIFT 17
#define FMC_ADC_CORE_CH4_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 17, 15)
#define FMC_ADC_CORE_CH4_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 17, 15)
#define FMC_ADC_CORE_CH4_OFFSET_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH4_OFFSET_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH4_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH4_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
PACKED struct FMC_ADC_CORE_WB {
/* [0x0]: REG Control register */
......
......@@ -1676,7 +1676,7 @@ fmc_adc_core_ch1_gain_reserved_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_offset_val_o[16:0]
fmc_adc_core_ch1_offset_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1693,7 +1693,7 @@ fmc_adc_core_ch1_offset_val_o[16:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_offset_reserved_o[14:0]
fmc_adc_core_ch1_offset_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1948,7 +1948,7 @@ fmc_adc_core_ch2_gain_reserved_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_offset_val_o[16:0]
fmc_adc_core_ch2_offset_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1965,7 +1965,7 @@ fmc_adc_core_ch2_offset_val_o[16:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_offset_reserved_o[14:0]
fmc_adc_core_ch2_offset_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2220,7 +2220,7 @@ fmc_adc_core_ch3_gain_reserved_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_offset_val_o[16:0]
fmc_adc_core_ch3_offset_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2237,7 +2237,7 @@ fmc_adc_core_ch3_offset_val_o[16:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_offset_reserved_o[14:0]
fmc_adc_core_ch3_offset_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2492,7 +2492,7 @@ fmc_adc_core_ch4_gain_reserved_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_offset_val_o[16:0]
fmc_adc_core_ch4_offset_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2509,7 +2509,7 @@ fmc_adc_core_ch4_offset_val_o[16:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_offset_reserved_o[14:0]
fmc_adc_core_ch4_offset_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -6277,7 +6277,7 @@ CH1_OFFSET
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[14:7]
RESERVED[15:8]
</td>
<td >
......@@ -6330,11 +6330,11 @@ RESERVED[14:7]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=7 class="td_field">
RESERVED[6:0]
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
VAL[16:16]
<td >
</td>
<td >
......@@ -7325,7 +7325,7 @@ CH2_OFFSET
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[14:7]
RESERVED[15:8]
</td>
<td >
......@@ -7378,11 +7378,11 @@ RESERVED[14:7]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=7 class="td_field">
RESERVED[6:0]
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
VAL[16:16]
<td >
</td>
<td >
......@@ -8373,7 +8373,7 @@ CH3_OFFSET
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[14:7]
RESERVED[15:8]
</td>
<td >
......@@ -8426,11 +8426,11 @@ RESERVED[14:7]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=7 class="td_field">
RESERVED[6:0]
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
VAL[16:16]
<td >
</td>
<td >
......@@ -9421,7 +9421,7 @@ CH4_OFFSET
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[14:7]
RESERVED[15:8]
</td>
<td >
......@@ -9474,11 +9474,11 @@ RESERVED[14:7]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=7 class="td_field">
RESERVED[6:0]
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
VAL[16:16]
<td >
</td>
<td >
......
......@@ -418,7 +418,7 @@ peripheral {
description = "Offset applied to all data coming from the ADC.";
prefix = "val";
type = SLV;
size = 17;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -428,7 +428,7 @@ peripheral {
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 15;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -519,7 +519,7 @@ peripheral {
description = "Offset applied to all data coming from the ADC.";
prefix = "val";
type = SLV;
size = 17;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -529,7 +529,7 @@ peripheral {
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 15;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -620,7 +620,7 @@ peripheral {
description = "Offset applied to all data coming from the ADC.";
prefix = "val";
type = SLV;
size = 17;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -630,7 +630,7 @@ peripheral {
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 15;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -721,7 +721,7 @@ peripheral {
description = "Offset applied to all data coming from the ADC.";
prefix = "val";
type = SLV;
size = 17;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -731,7 +731,7 @@ peripheral {
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 15;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......
......@@ -748,7 +748,7 @@
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
<file xil_pn:name="../../adc/rtl/offset_gain.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/offset_gain_s.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
......
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