hdl: minor improvement to simulation

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

hdl: minor improvement to simulation
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
cb190c6c · Dimitris Lampridis · 778a4401 · cb190c6c
Commit cb190c6c authored Aug 12, 2020 by Dimitris Lampridis
Hide whitespace changes
Inline Side-by-side

Showing with 2 additions and 0 deletions

main.sv hdl/testbench/spec_ref_design/main.sv +2 -0

No files found.
--- a/hdl/testbench/spec_ref_design/main.sv
+++ b/hdl/testbench/spec_ref_design/main.sv
@@ -279,6 +279,8 @@ module main;
      $display("<%t> START ACQ 1/4", $realtime);
      acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start

+      wait (DUT.cmp_fmc_adc_mezzanine.cmp_fmc_adc_100Ms_core.acq_in_wait_trig == 1);
+
      #200ns;

      acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFF); // soft trigger