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FMC ADC 100M 14b 4cha - Gateware
Commit c70ccee6 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: major rework of SVEC reference design 

 - Remove duplicate code and introduce a "for loop" generate for the two mezzanines.
 - Complete rework of timing constraints
 - Use SVEC BSP from WR for PLLs and reset
 - Replace xwb_clock_crossing with new xwb_clock_bridge
 - Redefine front panel LED functions, eliminate "heart-beat" LED
 - Fix bug where tm_time_valid was not re-synchronised
parent 877b153c
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hdl/syn/svec_ref_design_wr/syn_extra_steps.tcl
View file @ c70ccee6
......@@ -14,13 +14,19 @@ xilinx::project open $project_file
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
#xilinx::project set "Pack I/O Registers into IOBs" "Yes"
#xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
xilinx::project set "Placer Extra Effort Map" "Normal"
xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
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