Commit c4c3236b authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl: minor refactoring of SVEC reference design to align it with the SPEC one

parent 19d130b1
......@@ -24,8 +24,8 @@ xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
xilinx::project set "Placer Extra Effort Map" "Normal"
xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
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