Commit c4c3236b authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl: minor refactoring of SVEC reference design to align it with the SPEC one

parent 19d130b1
#===============================================================================
# The IO Location Constraints
# IO Constraints
#===============================================================================
#----------------------------------------
......@@ -7,7 +7,6 @@
#----------------------------------------
NET "vme_write_n_i" LOC = R1;
NET "vme_rst_n_i" LOC = P4;
#NET "vme_sysclk_i" LOC = P3;
NET "vme_retry_oe_o" LOC = R4;
NET "vme_retry_n_o" LOC = AB2;
NET "vme_lword_n_b" LOC = M7;
......@@ -106,9 +105,9 @@ NET "vme_addr_b[4]" LOC = N7;
NET "vme_addr_b[3]" LOC = N8;
NET "vme_addr_b[2]" LOC = AE1;
NET "vme_addr_b[1]" LOC = AE3;
NET "vme_write_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_rst_n_i" IOSTANDARD = "LVCMOS33";
#NET "vme_sysclk_i" IOSTANDARD = "LVCMOS33";
NET "vme_retry_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_retry_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_lword_n_b" IOSTANDARD = "LVCMOS33";
......@@ -117,130 +116,25 @@ NET "vme_iackin_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_iack_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[*]" IOSTANDARD = "LVCMOS33";
NET "vme_data_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_data_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_berr_o" IOSTANDARD = "LVCMOS33";
NET "vme_as_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_addr_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[7]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[6]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[5]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[4]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[3]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[2]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[1]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[*]" IOSTANDARD = "LVCMOS33";
NET "vme_gap_i" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[3]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[2]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[31]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[30]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[29]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[28]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[27]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[26]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[25]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[24]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[23]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[22]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[21]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[20]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[19]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[18]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[17]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[16]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[15]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[14]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[13]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[12]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[11]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[10]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[9]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[8]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[7]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[6]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[5]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[4]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[3]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[2]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[1]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[0]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[5]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[3]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[2]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[31]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[30]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[29]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[28]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[27]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[26]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[25]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[24]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[23]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[22]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[21]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[20]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[19]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[18]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[17]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[16]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[15]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[14]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[13]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[12]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[11]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[10]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[9]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[8]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[7]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[6]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[5]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[4]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[3]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[2]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[*]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[*]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[*]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[*]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# DDR IO standards and terminations
# DDR Memory
#----------------------------------------
NET "ddr_udqs_p_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_udqs_n_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_p_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_n_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_p_o[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_n_o[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_rzq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_we_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_udm_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_reset_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ras_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_odt_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ldm_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_cke_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_cas_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IN_TERM = NONE;
NET "ddr_ldqs_p_b[*]" IN_TERM = NONE;
NET "ddr_ldqs_n_b[*]" IN_TERM = NONE;
NET "ddr_udqs_p_b[*]" IN_TERM = NONE;
NET "ddr_udqs_n_b[*]" IN_TERM = NONE;
#----------------------------------------
# DDR0 (bank 4)
#----------------------------------------
NET "ddr_rzq_b[0]" LOC = L7;
NET "ddr_we_n_o[0]" LOC = F4;
NET "ddr_udqs_p_b[0]" LOC = K2;
......@@ -290,9 +184,7 @@ NET "ddr_a_o[2]" LOC = A3;
NET "ddr_a_o[1]" LOC = D3;
NET "ddr_a_o[0]" LOC = D4;
#----------------------------------------
# DDR1 (bank 5)
#----------------------------------------
NET "ddr_rzq_b[1]" LOC = G25;
NET "ddr_we_n_o[1]" LOC = E26;
NET "ddr_udqs_p_b[1]" LOC = K28;
......@@ -342,22 +234,46 @@ NET "ddr_a_o[16]" LOC = C30;
NET "ddr_a_o[15]" LOC = D30;
NET "ddr_a_o[14]" LOC = D28;
# DDR IO standards and terminations
NET "ddr_udqs_p_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_udqs_n_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_p_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_n_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_p_o[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_n_o[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_rzq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_we_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_udm_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_reset_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ras_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_odt_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ldm_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_cke_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_cas_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IN_TERM = NONE;
NET "ddr_ldqs_p_b[*]" IN_TERM = NONE;
NET "ddr_ldqs_n_b[*]" IN_TERM = NONE;
NET "ddr_udqs_p_b[*]" IN_TERM = NONE;
NET "ddr_udqs_n_b[*]" IN_TERM = NONE;
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "rst_n_i" LOC = AD28;
NET "rst_n_i" IOSTANDARD = "LVCMOS33";
NET "clk_20m_vcxo_i" LOC = V26;
NET "clk_125m_pllref_n_i" LOC = AB30;
NET "clk_125m_pllref_p_i" LOC = AB28;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" LOC = B19;
NET "clk_125m_gtp_n_i" LOC = A19;
NET "rst_n_i" IOSTANDARD = "LVCMOS33";
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
......@@ -368,7 +284,6 @@ NET "sfp_txp_o" LOC = B23;
NET "sfp_txn_o" LOC = A23;
NET "sfp_rxp_i" LOC = D22;
NET "sfp_rxn_i" LOC = C22;
NET "sfp_los_i" LOC = W25;
NET "sfp_mod_def0_i" LOC = Y26;
NET "sfp_mod_def1_b" LOC = Y27;
......@@ -376,6 +291,7 @@ NET "sfp_mod_def2_b" LOC = AA24;
NET "sfp_rate_select_o" LOC = W24;
NET "sfp_tx_disable_o" LOC = AA25;
NET "sfp_tx_fault_i" LOC = AA27;
NET "sfp_los_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS33";
......@@ -385,7 +301,7 @@ NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Clock controls
# DAC interfaces (for VCXO)
#----------------------------------------
NET "pll20dac_din_o" LOC = U28;
NET "pll20dac_sclk_o" LOC = AA28;
......@@ -393,6 +309,7 @@ NET "pll20dac_sync_n_o" LOC = N28;
NET "pll25dac_din_o" LOC = P25;
NET "pll25dac_sclk_o" LOC = N27;
NET "pll25dac_sync_n_o" LOC = P26;
NET "pll20dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS33";
......@@ -403,27 +320,30 @@ NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# SPI FLASH
#----------------------------------------
NET "SPI_NCS_O" LOC = AG27;
NET "SPI_NCS_O" IOSTANDARD = "LVCMOS33";
NET "SPI_SCLK_O" LOC = AG26;
NET "SPI_SCLK_O" IOSTANDARD = "LVCMOS33";
NET "SPI_MOSI_O" LOC = AH26;
NET "SPI_MOSI_O" IOSTANDARD = "LVCMOS33";
NET "SPI_MISO_I" LOC = AH27;
NET "SPI_MISO_I" IOSTANDARD = "LVCMOS33";
NET "spi_ncs_o" LOC = AG27;
NET "spi_sclk_o" LOC = AG26;
NET "spi_mosi_o" LOC = AH26;
NET "spi_miso_i" LOC = AH27;
NET "spi_ncs_o" IOSTANDARD = "LVCMOS33";
NET "spi_sclk_o" IOSTANDARD = "LVCMOS33";
NET "spi_mosi_o" IOSTANDARD = "LVCMOS33";
NET "spi_miso_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_txd_o" LOC = U27;
NET "uart_rxd_i" LOC = U25;
NET "uart_txd_o" IOSTANDARD = "LVCMOS33";
NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# 1-wire thermoeter + unique ID
# 1-wire thermometer + unique ID
#----------------------------------------
NET "carrier_onewire_b" LOC = AC30;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
......@@ -437,14 +357,10 @@ NET "fp_led_column_o[0]" LOC = AE30;
NET "fp_led_column_o[1]" LOC = AE27;
NET "fp_led_column_o[2]" LOC = AE28;
NET "fp_led_column_o[3]" LOC = AF28;
NET "fp_led_line_oen_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_oen_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[2]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[3]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_oen_o[*]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[*]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[*]" IOSTANDARD="LVCMOS33";
#----------------------------------------
# Front panel IOs
......@@ -460,6 +376,7 @@ NET "fp_term_en_o[1]" LOC = AB1;
NET "fp_term_en_o[2]" LOC = W5;
NET "fp_term_en_o[3]" LOC = W4;
NET "fp_term_en_o[4]" LOC = V4;
NET "fp_gpio1_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio2_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio3_o" IOSTANDARD = "LVCMOS33";
......@@ -467,64 +384,7 @@ NET "fp_gpio4_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio1_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio2_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio34_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[1]" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[2]" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[3]" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[4]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Debug LEDs
#----------------------------------------
#NET "dbg_led_n_o[4]" LOC = U7;
#NET "dbg_led_n_o[3]" LOC = AG1;
#NET "dbg_led_n_o[2]" LOC = AF1;
#NET "dbg_led_n_o[1]" LOC = R6;
#NET "dbg_led_n_o[4]" IOSTANDARD = "LVCMOS33";
#NET "dbg_led_n_o[3]" IOSTANDARD = "LVCMOS33";
#NET "dbg_led_n_o[2]" IOSTANDARD = "LVCMOS33";
#NET "dbg_led_n_o[1]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Switches and button
#----------------------------------------
#NET "pushbutton_i" LOC = P24;
#NET "noga_i[0]" LOC = AE26;
#NET "noga_i[1]" LOC = P23;
#NET "noga_i[2]" LOC = Y24;
#NET "noga_i[3]" LOC = Y23;
#NET "noga_i[4]" LOC = V23;
#NET "switch_i[0]" LOC = W22;
#NET "switch_i[1]" LOC = W21;
#NET "usega_i" LOC = Y22;
#NET "pushbutton_i" IOSTANDARD = "LVCMOS33";
#NET "noga_i[0]" IOSTANDARD = "LVCMOS33";
#NET "noga_i[1]" IOSTANDARD = "LVCMOS33";
#NET "noga_i[2]" IOSTANDARD = "LVCMOS33";
#NET "noga_i[3]" IOSTANDARD = "LVCMOS33";
#NET "noga_i[4]" IOSTANDARD = "LVCMOS33";
#NET "switch_i[0]" IOSTANDARD = "LVCMOS33";
#NET "switch_i[1]" IOSTANDARD = "LVCMOS33";
#NET "usega_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Inter-FPGA lines
#----------------------------------------
#NET "rsvd_b[0]" LOC = AG26;
#NET "rsvd_b[1]" LOC = AH26;
#NET "rsvd_b[2]" LOC = AG27;
#NET "rsvd_b[3]" LOC = AH27;
#NET "rsvd_b[4]" LOC = AK27;
#NET "rsvd_b[5]" LOC = AG28;
#NET "rsvd_b[6]" LOC = AJ28;
#NET "rsvd_b[7]" LOC = AK28;
#NET "rsvd_b[0]" IOSTANDARD = "LVCMOS33";
#NET "rsvd_b[1]" IOSTANDARD = "LVCMOS33";
#NET "rsvd_b[2]" IOSTANDARD = "LVCMOS33";
#NET "rsvd_b[3]" IOSTANDARD = "LVCMOS33";
#NET "rsvd_b[4]" IOSTANDARD = "LVCMOS33";
#NET "rsvd_b[5]" IOSTANDARD = "LVCMOS33";
#NET "rsvd_b[6]" IOSTANDARD = "LVCMOS33";
#NET "rsvd_b[7]" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[*]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# PCB revision
......@@ -534,17 +394,15 @@ NET "pcbrev_i[3]" LOC = AE17;
NET "pcbrev_i[2]" LOC = AD18;
NET "pcbrev_i[1]" LOC = AE20;
NET "pcbrev_i[0]" LOC = AD20;
NET "pcbrev_i[4]" IOSTANDARD = "LVCMOS25";
NET "pcbrev_i[3]" IOSTANDARD = "LVCMOS25";
NET "pcbrev_i[2]" IOSTANDARD = "LVCMOS25";
NET "pcbrev_i[1]" IOSTANDARD = "LVCMOS25";
NET "pcbrev_i[0]" IOSTANDARD = "LVCMOS25";
NET "pcbrev_i[*]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Carrier I2C EEPROM
#----------------------------------------
NET "carrier_scl_b" LOC = AC29;
NET "carrier_sda_b" LOC = AA30;
NET "carrier_scl_b" IOSTANDARD = "LVCMOS33";
NET "carrier_sda_b" IOSTANDARD = "LVCMOS33";
......@@ -552,42 +410,20 @@ NET "carrier_sda_b" IOSTANDARD = "LVCMOS33";
# FMC slots management
#----------------------------------------
NET "fmc_prsnt_m2c_n_i[0]" LOC = N30;
NET "fmc_scl_b[0]" LOC = P28;
NET "fmc_sda_b[0]" LOC = P30;
NET "fmc_prsnt_m2c_n_i[0]" IOSTANDARD = "LVCMOS33";
NET "fmc_scl_b[0]" IOSTANDARD = "LVCMOS33";
NET "fmc_sda_b[0]" IOSTANDARD = "LVCMOS33";
NET "fmc_prsnt_m2c_n_i[1]" LOC = AE29;
NET "fmc_scl_b[0]" LOC = P28;
NET "fmc_scl_b[1]" LOC = W29;
NET "fmc_sda_b[0]" LOC = P30;
NET "fmc_sda_b[1]" LOC = V30;
NET "fmc_prsnt_m2c_n_i[1]" IOSTANDARD = "LVCMOS33";
NET "fmc_scl_b[1]" IOSTANDARD = "LVCMOS33";
NET "fmc_sda_b[1]" IOSTANDARD = "LVCMOS33";
NET "fmc_prsnt_m2c_n_i[*]" IOSTANDARD = "LVCMOS33";
NET "fmc_scl_b[*]" IOSTANDARD = "LVCMOS33";
NET "fmc_sda_b[*]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# FMC slots
#----------------------------------------
# IO standards
NET "adc_ext_trigger_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_dco_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_fr_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_out?_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_spi_din_i[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_dout_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_sck_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_cs_adc_n_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_cs_dac?_n_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_dac_clr_n_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_led_acq_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_led_trig_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_ssr_ch?_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_si570_oe_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_si570_scl_b[*]" IOSTANDARD = "LVCMOS25";
NET "adc_si570_sda_b[*]" IOSTANDARD = "LVCMOS25";
NET "adc_one_wire_b[*]" IOSTANDARD = "LVCMOS25";
# FMC0
NET "adc_ext_trigger_n_i[0]" LOC = "A15";
NET "adc_ext_trigger_p_i[0]" LOC = "B15";
......@@ -722,48 +558,90 @@ NET "adc_si570_scl_b[1]" LOC = "AF21";
NET "adc_si570_sda_b[1]" LOC = "AE21";
NET "adc_one_wire_b[1]" LOC = "AD24";
#===============================================================================
# IO standards
NET "adc_ext_trigger_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_dco_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_fr_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_out?_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_spi_din_i[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_dout_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_sck_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_cs_adc_n_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_cs_dac?_n_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_dac_clr_n_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_led_acq_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_led_trig_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_ssr_ch?_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_si570_oe_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_si570_scl_b[*]" IOSTANDARD = "LVCMOS25";
NET "adc_si570_sda_b[*]" IOSTANDARD = "LVCMOS25";
NET "adc_one_wire_b[*]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# IOBs
#===============================================================================
#----------------------------------------
# Force PPS output to always be placed as IOB register
INST "cmp_xwrc_board_svec/*/wrapped_ppsgen/pps_out_o" IOB = FORCE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB=FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB=FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
#===============================================================================
# Timing constraints
# Timing Constraints
#===============================================================================
#----------------------------------------
# Clocks
#----------------------------------------
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "cmp_xwrc_board_svec/*/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
NET "adc_dco_n_i[0]" TNM_NET = adc0_dco_n_i;
TIMESPEC TS_adc0_dco_n_i = PERIOD "adc0_dco_n_i" 2.5 ns HIGH 50%;
NET "adc_dco_n_i[1]" TNM_NET = adc1_dco_n_i;
TIMESPEC TS_adc1_dco_n_i = PERIOD "adc1_dco_n_i" 2.5 ns HIGH 50%;
#----------------------------------------
# WR DMTD tweaks
#----------------------------------------
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
# DDR3
#----------------------------------------
# Xilinx MCB tweaks
#----------------------------------------
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "gen_ddr_ctrl*/*/c?_pll_lock" TIG;
NET "gen_ddr_ctrl*/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "gen_ddr_ctrl*/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
NET "gen_ddr_ctrl*/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
......@@ -771,21 +649,25 @@ NET "*/gc_reset_async_in" TIG;
NET "ddr_rst[*]" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# Declaration of domains
NET "clk_sys_62m5" TNM_NET = sys_clk_62_5;
NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "clk_ddr_333m" TNM_NET = ddr_clk_333m;
NET "cmp_xwrc_board_svec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
NET "gen_fmc_mezzanine[0].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs0_clk;
NET "gen_fmc_mezzanine[1].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs1_clk;
NET "clk_ddr_333m" TNM_NET = ddr_clk_333m;
NET "gen_ddr_ctrl[0].*/*/memc4_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_bank4_clk;
NET "gen_ddr_ctrl[1].*/*/memc5_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_bank5_clk;
TIMEGRP "ddr_clk" = "ddr_clk_333m" "ddr_bank4_clk" "ddr_bank5_clk";
TIMEGRP "ddr_clk" = "ddr_clk_333m" "ddr_bank4_clk" "ddr_bank5_clk";
TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM_NET = "sync_ffs";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
......@@ -802,6 +684,7 @@ TIMESPEC TS_phy_sync_ffs = FROM phy_clk TO "phy_sync_ffs" TIG;
TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG;
TIMESPEC TS_adc1_sync_ffs = FROM fs1_clk TO "adc1_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM_NET = "sync_reg";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
......
......@@ -24,8 +24,8 @@ xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
xilinx::project set "Placer Extra Effort Map" "Normal"
xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
......
......@@ -35,16 +35,16 @@ use UNISIM.vcomponents.all;
library work;
use work.vme64x_pkg.all;
use work.ddr3_ctrl_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.fmc_adc_mezzanine_pkg.all;
use work.synthesis_descriptor.all;
use work.vme64x_pkg.all;
use work.timetag_core_pkg.all;
use work.carrier_csr_wbgen2_pkg.all;
use work.wr_board_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_svec_pkg.all;
entity svec_ref_fmc_adc_100Ms is
......@@ -154,24 +154,24 @@ entity svec_ref_fmc_adc_100Ms is
------------------------------------------
-- DDR (banks 4 and 5)
------------------------------------------
ddr_we_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_udqs_p_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_udqs_n_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_udm_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_reset_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_ras_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_odt_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_ldqs_p_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_ldqs_n_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_ldm_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_cke_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_ck_p_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_ck_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_a_o : out std_logic_vector(14*g_NB_FMC_SLOTS-1 downto 0);
ddr_ba_o : out std_logic_vector(3*g_NB_FMC_SLOTS-1 downto 0);
ddr_cas_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_ck_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_ck_p_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_cke_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_dq_b : inout std_logic_vector(16*g_NB_FMC_SLOTS-1 downto 0);
ddr_ba_o : out std_logic_vector(3*g_NB_FMC_SLOTS-1 downto 0);
ddr_a_o : out std_logic_vector(14*g_NB_FMC_SLOTS-1 downto 0);
ddr_ldm_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_ldqs_n_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_ldqs_p_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_odt_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_ras_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_reset_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_rzq_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_udm_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_udqs_n_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_udqs_p_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
ddr_we_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0);
------------------------------------------
-- FMC slots
......@@ -262,14 +262,13 @@ architecture rtl of svec_ref_fmc_adc_100Ms is
-- SDB meta info
constant c_SDB_GIT_REPO_URL : integer := c_NUM_WB_SLAVES;
constant c_SDB_SYNTHESIS : integer := c_NUM_WB_SLAVES + 1;
constant c_SDB_INTEGRATE : integer := c_NUM_WB_SLAVES + 2;
-- Devices sdb description
constant c_wb_svec_csr_sdb : t_sdb_device := (
constant c_WB_SVEC_CSR_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
......@@ -281,11 +280,11 @@ architecture rtl of svec_ref_fmc_adc_100Ms is
date => x"20121116",
name => "WB-SVEC-CSR ")));
constant c_wb_ddr_dat_sdb : t_sdb_device := (
constant c_WB_DDR_DAT_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
......@@ -297,11 +296,11 @@ architecture rtl of svec_ref_fmc_adc_100Ms is
date => x"20130704",
name => "WB-DDR-Data-Access ")));
constant c_wb_ddr_adr_sdb : t_sdb_device := (
constant c_WB_DDR_ADR_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
......@@ -315,38 +314,27 @@ architecture rtl of svec_ref_fmc_adc_100Ms is
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_fmc0_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
constant c_fmc1_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
constant c_wr_core_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_FMC0_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
constant c_FMC1_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
constant c_WR_CORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
-- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- sdb integration record
constant c_integration_sdb : t_sdb_integration := (
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"5c01a632", -- echo "svec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00050000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20181025", -- yyyymmdd
name => "svec_fmcadc100m14b "));
-- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 2 downto 0) :=
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) :=
(
c_WB_SLAVE_SVEC_CSR => f_sdb_embed_device(c_wb_svec_csr_sdb, x"00001200"),