Commit bced5daf authored by mcattin's avatar mcattin

Mezzanine 1-wire implemented and working.

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@71 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent ad44e580
......@@ -345,14 +345,14 @@ architecture rtl of fmc_adc_100Ms_core is
signal multishot_buffer_sel : std_logic;
-- Multi-shot mode
constant c_DPRAM_DEPTH : integer := 13;
signal dpram_addra_cnt : unsigned(c_DPRAM_DEPTH-1 downto 0);
signal dpram_addra_trig : unsigned(c_DPRAM_DEPTH-1 downto 0);
signal dpram_addra_post_done : unsigned(c_DPRAM_DEPTH-1 downto 0);
signal dpram_addrb_cnt : unsigned(c_DPRAM_DEPTH-1 downto 0);
signal dpram_dout : std_logic_vector(63 downto 0);
signal dpram_valid : std_logic;
signal dpram_valid_t : std_logic;
constant c_DPRAM_DEPTH : integer := 13;
signal dpram_addra_cnt : unsigned(c_DPRAM_DEPTH-1 downto 0);
signal dpram_addra_trig : unsigned(c_DPRAM_DEPTH-1 downto 0);
signal dpram_addra_post_done : unsigned(c_DPRAM_DEPTH-1 downto 0);
signal dpram_addrb_cnt : unsigned(c_DPRAM_DEPTH-1 downto 0);
signal dpram_dout : std_logic_vector(63 downto 0);
signal dpram_valid : std_logic;
signal dpram_valid_t : std_logic;
signal dpram0_dina : std_logic_vector(63 downto 0);
signal dpram0_addra : std_logic_vector(c_DPRAM_DEPTH-1 downto 0);
......@@ -761,8 +761,8 @@ begin
begin
if rising_edge(sys_clk_i) then
if sys_rst_n_i = '0' then
shots_cnt <= to_unsigned(0, shots_cnt'length);
shots_done <= '0';
shots_cnt <= to_unsigned(0, shots_cnt'length);
shots_done <= '0';
single_shot <= '0';
else
if acq_start = '1' then
......@@ -773,7 +773,7 @@ begin
elsif shots_decr = '1' then
shots_cnt <= shots_cnt - 1;
end if;
if shots_value = std_logic_vector(to_unsigned(1,shots_value'length)) then
if shots_value = std_logic_vector(to_unsigned(1, shots_value'length)) then
single_shot <= '1';
else
single_shot <= '0';
......@@ -957,8 +957,8 @@ begin
begin
if rising_edge(sys_clk_i) then
if sys_rst_n_i = '0' then
dpram_addra_cnt <= (others => '0');
dpram_addra_trig <= (others => '0');
dpram_addra_cnt <= (others => '0');
dpram_addra_trig <= (others => '0');
dpram_addra_post_done <= (others => '0');
else
if shots_decr = '1' then
......@@ -1018,7 +1018,7 @@ begin
else
if post_trig_done = '1' then
dpram_addrb_cnt <= dpram_addra_trig - unsigned(pre_trig_value(c_DPRAM_DEPTH-1 downto 0));
dpram_valid_t <= '1';
dpram_valid_t <= '1';
elsif (dpram_addrb_cnt = dpram_addra_post_done) then
dpram_valid_t <= '0';
else
......@@ -1050,8 +1050,20 @@ begin
valid => wb_ddr_fifo_valid
);
wb_ddr_fifo_din <= sync_fifo_dout(63 downto 0) when single_shot = '1' else dpram_dout;
wb_ddr_fifo_wr_en <= samples_wr_en when single_shot = '1' else dpram_valid;
p_wb_ddr_fifo_input : process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
if single_shot = '1' then
wb_ddr_fifo_din <= sync_fifo_dout(63 downto 0);
wb_ddr_fifo_wr_en <= samples_wr_en;
else
wb_ddr_fifo_din <= dpram_dout;
wb_ddr_fifo_wr_en <= dpram_valid;
end if;
end if;
end process p_wb_ddr_fifo_input;
--wb_ddr_fifo_din <= sync_fifo_dout(63 downto 0) when single_shot = '1' else dpram_dout;
--wb_ddr_fifo_wr_en <= samples_wr_en when single_shot = '1' else dpram_valid;
wb_ddr_fifo_wr <= wb_ddr_fifo_wr_en and sync_fifo_valid and not(wb_ddr_fifo_full);
wb_ddr_fifo_rd <= wb_ddr_fifo_dreq and not(wb_ddr_fifo_empty) and not(wb_ddr_stall_t);
......@@ -1102,7 +1114,7 @@ begin
if wb_ddr_fifo_valid = '1' then
wb_ddr_cyc_o <= '1';
wb_ddr_we_o <= '1';
--elsif (wb_ddr_fifo_empty = '1') and (acq_end = '1') then
--elsif (wb_ddr_fifo_empty = '1') and (acq_end = '1') then
elsif (wb_ddr_fifo_empty = '1') and (acq_fsm_state = "001") then
wb_ddr_cyc_o <= '0';
wb_ddr_we_o <= '0';
......
......@@ -49,6 +49,10 @@ entity spec_top_fmc_adc_100Ms is
led_red_o : out std_logic;
led_green_o : out std_logic;
-- Auxiliary pins
aux_leds_o : out std_logic_vector(3 downto 0);
aux_buttons_i : in std_logic_vector(1 downto 0);
-- PCB version
pcb_ver_i : in std_logic_vector(3 downto 0);
......@@ -130,8 +134,10 @@ entity spec_top_fmc_adc_100Ms is
gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control
gpio_si570_oe_o : out std_logic; -- Si570 (programmable oscillator) output enable
si570_thermo_scl_b : inout std_logic; -- I2C bus clock (Si570 and MCP9801 thermometer)
si570_thermo_sda_b : inout std_logic; -- I2C bus data (Si570 and MCP9801 thermometer)
si570_scl_b : inout std_logic; -- I2C bus clock (Si570)
si570_sda_b : inout std_logic; -- I2C bus data (Si570)
one_wire_b : inout std_logic; -- 1-wire interface (DS18B20 thermometer + unique ID)
prsnt_m2c_n_i : in std_logic -- Mezzanine present (active low)
);
......@@ -279,7 +285,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
constant c_BITSTREAM_DATE : std_logic_vector(31 downto 0) := X"4D6BBE3E"; -- UTC time
constant c_BAR0_APERTURE : integer := 18; -- nb of bits for 32-bit word address (= byte aperture - 2)
constant c_CSR_WB_SLAVES_NB : integer := 10;
constant c_CSR_WB_SLAVES_NB : integer := 11;
constant c_CSR_WB_DMA_CONFIG : integer := 0;
constant c_CSR_WB_CARRIER_SPI : integer := 1;
......@@ -291,6 +297,9 @@ architecture rtl of spec_top_fmc_adc_100Ms is
constant c_CSR_WB_FMC_SPI : integer := 7;
constant c_CSR_WB_FMC_I2C : integer := 8;
constant c_CSR_WB_FMC_ADC_CORE : integer := 9;
constant c_CSR_WB_FMC_ONE_WIRE : integer := 10;
constant c_FMC_ONE_WIRE_NB : integer := 1;
------------------------------------------------------------------------------
-- Signals declaration
......@@ -365,13 +374,13 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal irq_to_gn4124 : std_logic;
signal irq_sources_2_led : std_logic_vector(1 downto 0);
-- Mezzanine I2C for Si570 and thermometer
signal si570_thermo_scl_in : std_logic;
signal si570_thermo_scl_out : std_logic;
signal si570_thermo_scl_oe_n : std_logic;
signal si570_thermo_sda_in : std_logic;
signal si570_thermo_sda_out : std_logic;
signal si570_thermo_sda_oe_n : std_logic;
-- Mezzanine I2C for Si570
signal si570_scl_in : std_logic;
signal si570_scl_out : std_logic;
signal si570_scl_oe_n : std_logic;
signal si570_sda_in : std_logic;
signal si570_sda_out : std_logic;
signal si570_sda_oe_n : std_logic;
-- LED control from carrier CSR register
signal led_red : std_logic;
......@@ -396,8 +405,15 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal spi_din_t : std_logic_vector(3 downto 0);
signal spi_ss_t : std_logic_vector(7 downto 0);
-- Mezzanine 1-wire
signal owr_pwren : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
signal owr_en : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
signal owr_i : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
-- Tests
signal test_dpram_we : std_logic;
signal led_cnt : unsigned(26 downto 0);
signal led_pps : std_logic;
begin
......@@ -566,6 +582,7 @@ begin
-- 0x70000 -> Mezzanine SPI master
-- 0x80000 -> Mezzanine I2C master
-- 0x90000 -> Mezzanine ADC core
-- 0xA0000 -> Mezzanine 1-wire master
------------------------------------------------------------------------------
cmp_csr_wb_addr_decoder : wb_addr_decoder
generic map (
......@@ -728,7 +745,6 @@ begin
------------------------------------------------------------------------------
-- Mezzanine I2C
-- Si570 control
-- Thermometer control
--
-- Note: I2C registers are 8-bit wide, but accessed as 32-bit registers
------------------------------------------------------------------------------
......@@ -747,23 +763,23 @@ begin
wb_ack_o => wb_ack(c_CSR_WB_FMC_I2C),
wb_int_o => open,
scl_pad_i => si570_thermo_scl_in,
scl_pad_o => si570_thermo_scl_out,
scl_padoen_o => si570_thermo_scl_oe_n,
sda_pad_i => si570_thermo_sda_in,
sda_pad_o => si570_thermo_sda_out,
sda_padoen_o => si570_thermo_sda_oe_n
scl_pad_i => si570_scl_in,
scl_pad_o => si570_scl_out,
scl_padoen_o => si570_scl_oe_n,
sda_pad_i => si570_sda_in,
sda_pad_o => si570_sda_out,
sda_padoen_o => si570_sda_oe_n
);
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_FMC_I2C) <= '0';
-- Tri-state buffer for SDA and SCL
si570_thermo_scl_b <= si570_thermo_scl_out when si570_thermo_scl_oe_n = '0' else 'Z';
si570_thermo_scl_in <= si570_thermo_scl_b;
si570_scl_b <= si570_scl_out when si570_scl_oe_n = '0' else 'Z';
si570_scl_in <= si570_scl_b;
si570_thermo_sda_b <= si570_thermo_sda_out when si570_thermo_sda_oe_n = '0' else 'Z';
si570_thermo_sda_in <= si570_thermo_sda_b;
si570_sda_b <= si570_sda_out when si570_sda_oe_n = '0' else 'Z';
si570_sda_in <= si570_sda_b;
------------------------------------------------------------------------------
-- ADC core
......@@ -821,6 +837,41 @@ begin
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_FMC_ADC_CORE) <= '0';
------------------------------------------------------------------------------
-- Mezzanine 1-wire master
-- DS18B20 (thermometer + unique ID)
------------------------------------------------------------------------------
cmp_fmc_onewire : wb_onewire_master
generic map(
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0"
)
port map(
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
wb_cyc_i => wb_cyc(c_CSR_WB_FMC_ONE_WIRE),
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_adr_i => wb_adr(1 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_FMC_ONE_WIRE * 32 + 31 downto 32 * c_CSR_WB_FMC_ONE_WIRE),
wb_ack_o => wb_ack(c_CSR_WB_FMC_ONE_WIRE),
wb_int_o => open,
owr_pwren_o => owr_pwren,
owr_en_o => owr_en,
owr_i => owr_i
);
one_wire_b <= '0' when owr_en(0) = '1' else 'Z';
owr_i(0) <= one_wire_b;
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_FMC_ONE_WIRE) <= '0';
------------------------------------------------------------------------------
-- Interrupt stuff
------------------------------------------------------------------------------
......@@ -962,5 +1013,36 @@ begin
------------------------------------------------------------------------------
GPIO(1) <= '0';
------------------------------------------------------------------------------
-- Blink auxiliary LEDs
------------------------------------------------------------------------------
p_led_cnt : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if (sys_rst_n = '0') then
led_cnt <= (others => '0');
led_pps <= '0';
elsif (led_cnt = X"773593F") then
led_cnt <= (others => '0');
led_pps <= not(led_pps);
else
led_cnt <= led_cnt + 1;
end if;
end if;
end process p_led_cnt;
p_led_blink : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if sys_rst_n = '0' then
aux_leds_o <= X"5";
elsif led_pps = '1' then
aux_leds_o <= X"A";
else
aux_leds_o <= X"5";
end if;
end if;
end process p_led_blink;
end rtl;
......@@ -334,10 +334,13 @@ NET "gpio_ssr_ch4_o[6]" IOSTANDARD = "LVCMOS25";
NET "gpio_si570_oe_o" LOC = AB5; # LA06_N
NET "gpio_si570_oe_o" IOSTANDARD = "LVCMOS25";
NET "si570_thermo_scl_b" LOC = U12; # LA18_N
NET "si570_thermo_scl_b" IOSTANDARD = "LVCMOS25";
NET "si570_thermo_sda_b" LOC = T12; # LA18_P
NET "si570_thermo_sda_b" IOSTANDARD = "LVCMOS25";
NET "si570_scl_b" LOC = U12; # LA18_N
NET "si570_scl_b" IOSTANDARD = "LVCMOS25";
NET "si570_sda_b" LOC = T12; # LA18_P
NET "si570_sda_b" IOSTANDARD = "LVCMOS25";
NET "one_wire_b" LOC = Y18; # LA29_N
NET "one_wire_b" IOSTANDARD = "LVCMOS25";
NET "prsnt_m2c_n_i" LOC = AB14; # PRSNT_M2C_L
NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
......@@ -354,8 +357,6 @@ NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
#NET "LA23_N" IOSTANDARD = "LVCMOS25";
#NET "LA23_P" LOC = AA16;
#NET "LA23_P" IOSTANDARD = "LVCMOS25";
#NET "LA29_N" LOC = Y18;
#NET "LA29_N" IOSTANDARD = "LVCMOS25";
#NET "TDO_FROM_FMC" LOC = F9;
#NET "TDO_FROM_FMC" IOSTANDARD = "LVCMOS25";
......@@ -527,19 +528,18 @@ NET "DDR3_DQ[15]" IOSTANDARD = "SSTL15_II";
#----------------------------------------
# Buttons and LEDs
#----------------------------------------
#NET "AUX_PINS[0]" LOC = C22; # Button PB1
#NET "AUX_PINS[0]" IOSTANDARD = "LVCMOS18";
#NET "AUX_PINS[1]" LOC = D21; # Button PB2
#NET "AUX_PINS[1]" IOSTANDARD = "LVCMOS18";
#NET "AUX_PINS[2]" LOC = G19; # LED LD2
#NET "AUX_PINS[2]" IOSTANDARD = "LVCMOS18";
#NET "AUX_PINS[3]" LOC = F20; # LED LD3
#NET "AUX_PINS[3]" IOSTANDARD = "LVCMOS18";
#NET "AUX_PINS[4]" LOC = F18; # LED LD4
#NET "AUX_PINS[4]" IOSTANDARD = "LVCMOS18";
#NET "AUX_PINS[5]" LOC = C20; # LED LD5
#NET "AUX_PINS[5]" IOSTANDARD = "LVCMOS18";
NET "AUX_BUTTONS_I[0]" LOC = C22;
NET "AUX_BUTTONS_I[0]" IOSTANDARD = "LVCMOS18";
NET "AUX_BUTTONS_I[1]" LOC = D21;
NET "AUX_BUTTONS_I[1]" IOSTANDARD = "LVCMOS18";
NET "AUX_LEDS_O[0]" LOC = G19;
NET "AUX_LEDS_O[0]" IOSTANDARD = "LVCMOS18";
NET "AUX_LEDS_O[1]" LOC = F20;
NET "AUX_LEDS_O[1]" IOSTANDARD = "LVCMOS18";
NET "AUX_LEDS_O[2]" LOC = F18;
NET "AUX_LEDS_O[2]" IOSTANDARD = "LVCMOS18";
NET "AUX_LEDS_O[3]" LOC = C20;
NET "AUX_LEDS_O[3]" IOSTANDARD = "LVCMOS18";
#===============================================================================
......
......@@ -716,6 +716,7 @@
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......
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