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FMC ADC 100M 14b 4cha - Gateware
Commits
b536d7b4
Commit
b536d7b4
authored
Jan 09, 2014
by
Matthieu Cattin
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hdl: Move fmc eic and timetag core to mezzanine (behind the wb bridge).
-> memory map changed!
parent
f0c9a78a
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4 changed files
with
249 additions
and
453 deletions
+249
-453
fmc_adc_mezzanine.vhd
hdl/adc/rtl/fmc_adc_mezzanine.vhd
+170
-16
fmc_adc_mezzanine_pkg.vhd
hdl/adc/rtl/fmc_adc_mezzanine_pkg.vhd
+6
-9
spec_top_fmc_adc_100Ms.vhd
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
+35
-182
svec_top_fmc_adc_100Ms.vhd
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
+38
-246
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hdl/adc/rtl/fmc_adc_mezzanine.vhd
View file @
b536d7b4
...
...
@@ -78,14 +78,11 @@ entity fmc_adc_mezzanine is
wb_ddr_ack_i
:
in
std_logic
;
wb_ddr_stall_i
:
in
std_logic
;
-- Events output pulses (for interrupt and time-stamping)
trigger_p_o
:
out
std_logic
;
acq_start_p_o
:
out
std_logic
;
acq_stop_p_o
:
out
std_logic
;
acq_end_p_o
:
out
std_logic
;
-- Trigger time-tag input
trigger_tag_i
:
t_timetag
;
-- Interrupts
ddr_wr_fifo_empty_i
:
in
std_logic
;
trig_irq_o
:
out
std_logic
;
acq_end_irq_o
:
out
std_logic
;
eic_irq_o
:
out
std_logic
;
-- FMC interface
ext_trigger_p_i
:
in
std_logic
;
-- External trigger
...
...
@@ -131,6 +128,28 @@ end fmc_adc_mezzanine;
architecture
rtl
of
fmc_adc_mezzanine
is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component
fmc_adc_eic
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
wb_int_o
:
out
std_logic
;
irq_trig_i
:
in
std_logic
;
irq_acq_end_i
:
in
std_logic
);
end
component
fmc_adc_eic
;
------------------------------------------------------------------------------
-- SDB crossbar constants declaration
--
...
...
@@ -138,7 +157,7 @@ architecture rtl of fmc_adc_mezzanine is
------------------------------------------------------------------------------
-- Number of master port(s) on the wishbone crossbar
constant
c_NUM_WB_MASTERS
:
integer
:
=
5
;
constant
c_NUM_WB_MASTERS
:
integer
:
=
7
;
-- Number of slave port(s) on the wishbone crossbar
constant
c_NUM_WB_SLAVES
:
integer
:
=
1
;
...
...
@@ -152,6 +171,8 @@ architecture rtl of fmc_adc_mezzanine is
constant
c_WB_SLAVE_FMC_I2C
:
integer
:
=
2
;
-- Mezzanine I2C controller
constant
c_WB_SLAVE_FMC_ADC
:
integer
:
=
3
;
-- Mezzanine ADC core
constant
c_WB_SLAVE_FMC_ONEWIRE
:
integer
:
=
4
;
-- Mezzanine onewire interface
constant
c_WB_SLAVE_FMC_EIC
:
integer
:
=
5
;
-- Mezzanine interrupt controller
constant
c_WB_SLAVE_TIMETAG
:
integer
:
=
6
;
-- Mezzanine timetag core
-- Devices sdb description
constant
c_wb_adc_csr_sdb
:
t_sdb_device
:
=
(
...
...
@@ -170,17 +191,51 @@ architecture rtl of fmc_adc_mezzanine is
date
=>
x"20121116"
,
name
=>
"WB-FMC-ADC-Core "
)));
constant
c_wb_timetag_sdb
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"4"
,
-- 32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"000000000000007F"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000604"
,
version
=>
x"00000001"
,
date
=>
x"20121116"
,
name
=>
"WB-Timetag-Core "
)));
constant
c_wb_fmc_adc_eic_sdb
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"4"
,
-- 32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"000000000000000F"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"26ec6086"
,
-- "WB-FMC-ADC.EIC " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20131204"
,
name
=>
"WB-FMC-ADC.EIC "
)));
-- sdb header address
constant
c_SDB_ADDRESS
:
t_wishbone_address
:
=
x"00000000"
;
-- Wishbone crossbar layout
constant
c_INTERCONNECT_LAYOUT
:
t_sdb_record_array
(
4
downto
0
)
:
=
constant
c_INTERCONNECT_LAYOUT
:
t_sdb_record_array
(
6
downto
0
)
:
=
(
0
=>
f_sdb_embed_device
(
c_xwb_i2c_master_sdb
,
x"00001000"
),
1
=>
f_sdb_embed_device
(
c_xwb_spi_sdb
,
x"00001100"
),
2
=>
f_sdb_embed_device
(
c_xwb_i2c_master_sdb
,
x"00001200"
),
3
=>
f_sdb_embed_device
(
c_wb_adc_csr_sdb
,
x"00001300"
),
4
=>
f_sdb_embed_device
(
c_xwb_onewire_master_sdb
,
x"00001400"
)
4
=>
f_sdb_embed_device
(
c_xwb_onewire_master_sdb
,
x"00001400"
),
5
=>
f_sdb_embed_device
(
c_wb_fmc_adc_eic_sdb
,
x"00001500"
),
6
=>
f_sdb_embed_device
(
c_wb_timetag_sdb
,
x"00001600"
)
);
...
...
@@ -220,6 +275,19 @@ architecture rtl of fmc_adc_mezzanine is
signal
mezz_owr_en
:
std_logic_vector
(
0
downto
0
);
signal
mezz_owr_i
:
std_logic_vector
(
0
downto
0
);
-- Interrupts (eic)
signal
ddr_wr_fifo_empty_d
:
std_logic
;
signal
ddr_wr_fifo_empty_p
:
std_logic
;
signal
acq_end_irq_p
:
std_logic
;
signal
acq_end_extend
:
std_logic
;
-- Time-tagging core
signal
trigger_p
:
std_logic
;
signal
acq_start_p
:
std_logic
;
signal
acq_stop_p
:
std_logic
;
signal
acq_end_p
:
std_logic
;
signal
trigger_tag
:
t_timetag
;
begin
...
...
@@ -398,12 +466,12 @@ begin
wb_ddr_ack_i
=>
wb_ddr_ack_i
,
wb_ddr_stall_i
=>
wb_ddr_stall_i
,
trigger_p_o
=>
trigger_p
_o
,
acq_start_p_o
=>
acq_start_p
_o
,
acq_stop_p_o
=>
acq_stop_p
_o
,
acq_end_p_o
=>
acq_end_p
_o
,
trigger_p_o
=>
trigger_p
,
acq_start_p_o
=>
acq_start_p
,
acq_stop_p_o
=>
acq_stop_p
,
acq_end_p_o
=>
acq_end_p
,
trigger_tag_i
=>
trigger_tag
_i
,
trigger_tag_i
=>
trigger_tag
,
ext_trigger_p_i
=>
ext_trigger_p_i
,
ext_trigger_n_i
=>
ext_trigger_n_i
,
...
...
@@ -461,4 +529,90 @@ begin
mezz_one_wire_b
<=
'0'
when
mezz_owr_en
(
0
)
=
'1'
else
'Z'
;
mezz_owr_i
(
0
)
<=
mezz_one_wire_b
;
------------------------------------------------------------------------------
-- FMC0 interrupt controller
------------------------------------------------------------------------------
cmp_fmc0_eic
:
fmc_adc_eic
port
map
(
rst_n_i
=>
sys_rst_n_i
,
clk_sys_i
=>
sys_clk_i
,
wb_adr_i
=>
cnx_master_out
(
c_WB_SLAVE_FMC_EIC
)
.
adr
(
3
downto
2
),
-- cnx_master_out.adr is byte address
wb_dat_i
=>
cnx_master_out
(
c_WB_SLAVE_FMC_EIC
)
.
dat
,
wb_dat_o
=>
cnx_master_in
(
c_WB_SLAVE_FMC_EIC
)
.
dat
,
wb_cyc_i
=>
cnx_master_out
(
c_WB_SLAVE_FMC_EIC
)
.
cyc
,
wb_sel_i
=>
cnx_master_out
(
c_WB_SLAVE_FMC_EIC
)
.
sel
,
wb_stb_i
=>
cnx_master_out
(
c_WB_SLAVE_FMC_EIC
)
.
stb
,
wb_we_i
=>
cnx_master_out
(
c_WB_SLAVE_FMC_EIC
)
.
we
,
wb_ack_o
=>
cnx_master_in
(
c_WB_SLAVE_FMC_EIC
)
.
ack
,
wb_stall_o
=>
cnx_master_in
(
c_WB_SLAVE_FMC_EIC
)
.
stall
,
wb_int_o
=>
eic_irq_o
,
irq_trig_i
=>
trigger_p
,
irq_acq_end_i
=>
acq_end_irq_p
);
-- Unused wishbone signals
cnx_master_in
(
c_WB_SLAVE_FMC_EIC
)
.
err
<=
'0'
;
cnx_master_in
(
c_WB_SLAVE_FMC_EIC
)
.
rty
<=
'0'
;
cnx_master_in
(
c_WB_SLAVE_FMC_EIC
)
.
int
<=
'0'
;
-- Detects end of adc core writing to ddr
p_ddr_wr_fifo_empty
:
process
(
sys_clk_i
)
begin
if
rising_edge
(
sys_clk_i
)
then
ddr_wr_fifo_empty_d
<=
ddr_wr_fifo_empty_i
;
end
if
;
end
process
p_ddr_wr_fifo_empty
;
ddr_wr_fifo_empty_p
<=
ddr_wr_fifo_empty_i
and
not
(
ddr_wr_fifo_empty_d
);
-- End of acquisition interrupt generation
p_acq_end_extend
:
process
(
sys_clk_i
)
begin
if
rising_edge
(
sys_clk_i
)
then
if
sys_rst_n_i
=
'0'
then
acq_end_extend
<=
'0'
;
elsif
acq_end_p
=
'1'
then
acq_end_extend
<=
'1'
;
elsif
ddr_wr_fifo_empty_p
=
'1'
then
acq_end_extend
<=
'0'
;
end
if
;
end
if
;
end
process
p_acq_end_extend
;
acq_end_irq_p
<=
ddr_wr_fifo_empty_p
and
acq_end_extend
;
trig_irq_o
<=
trigger_p
;
acq_end_irq_o
<=
acq_end_irq_p
;
------------------------------------------------------------------------------
-- Time-tagging core
------------------------------------------------------------------------------
cmp_timetag_core
:
timetag_core
port
map
(
clk_i
=>
sys_clk_i
,
rst_n_i
=>
sys_rst_n_i
,
trigger_p_i
=>
trigger_p
,
acq_start_p_i
=>
acq_start_p
,
acq_stop_p_i
=>
acq_stop_p
,
acq_end_p_i
=>
acq_end_p
,
trig_tag_o
=>
trigger_tag
,
wb_adr_i
=>
cnx_master_out
(
c_WB_SLAVE_TIMETAG
)
.
adr
(
6
downto
2
),
-- cnx_master_out.adr is byte address
wb_dat_i
=>
cnx_master_out
(
c_WB_SLAVE_TIMETAG
)
.
dat
,
wb_dat_o
=>
cnx_master_in
(
c_WB_SLAVE_TIMETAG
)
.
dat
,
wb_cyc_i
=>
cnx_master_out
(
c_WB_SLAVE_TIMETAG
)
.
cyc
,
wb_sel_i
=>
cnx_master_out
(
c_WB_SLAVE_TIMETAG
)
.
sel
,
wb_stb_i
=>
cnx_master_out
(
c_WB_SLAVE_TIMETAG
)
.
stb
,
wb_we_i
=>
cnx_master_out
(
c_WB_SLAVE_TIMETAG
)
.
we
,
wb_ack_o
=>
cnx_master_in
(
c_WB_SLAVE_TIMETAG
)
.
ack
);
-- Unused wishbone signals
cnx_master_in
(
c_WB_SLAVE_TIMETAG
)
.
err
<=
'0'
;
cnx_master_in
(
c_WB_SLAVE_TIMETAG
)
.
rty
<=
'0'
;
cnx_master_in
(
c_WB_SLAVE_TIMETAG
)
.
stall
<=
'0'
;
cnx_master_in
(
c_WB_SLAVE_TIMETAG
)
.
int
<=
'0'
;
end
rtl
;
hdl/adc/rtl/fmc_adc_mezzanine_pkg.vhd
View file @
b536d7b4
...
...
@@ -53,7 +53,7 @@ package fmc_adc_mezzanine_pkg is
component
fmc_adc_mezzanine
generic
(
g_multishot_ram_size
:
natural
:
=
2048
;
g_carrier_type
:
string
:
=
"SPEC"
g_carrier_type
:
string
:
=
"SPEC"
);
port
(
-- Clock, reset
...
...
@@ -82,14 +82,11 @@ package fmc_adc_mezzanine_pkg is
wb_ddr_ack_i
:
in
std_logic
;
wb_ddr_stall_i
:
in
std_logic
;
-- Events output pulses (for interrupt and time-stamping)
trigger_p_o
:
out
std_logic
;
acq_start_p_o
:
out
std_logic
;
acq_stop_p_o
:
out
std_logic
;
acq_end_p_o
:
out
std_logic
;
-- Trigger time-tag input
trigger_tag_i
:
t_timetag
;
-- Interrupt
ddr_wr_fifo_empty_i
:
in
std_logic
;
trig_irq_o
:
out
std_logic
;
acq_end_irq_o
:
out
std_logic
;
eic_irq_o
:
out
std_logic
;
-- FMC interface
ext_trigger_p_i
:
in
std_logic
;
-- External trigger
...
...
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @
b536d7b4
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hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
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b536d7b4
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