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FMC ADC 100M 14b 4cha - Gateware
Commit b4cf7521 authored by Matthieu Cattin's avatar Matthieu Cattin
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hdl: Update wbgen wishbone interfaces (port name change).

parent dbd5e841
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hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ b4cf7521
...@@ -143,15 +143,16 @@ architecture rtl of fmc_adc_100Ms_core is ...@@ -143,15 +143,16 @@ architecture rtl of fmc_adc_100Ms_core is
component fmc_adc_100Ms_csr component fmc_adc_100Ms_csr
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
wb_clk_i : in std_logic; clk_sys_i : in std_logic;
wb_addr_i : in std_logic_vector(4 downto 0); wb_adr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic; wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0); wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic; wb_stb_i : in std_logic;
wb_we_i : in std_logic; wb_we_i : in std_logic;
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk_i : in std_logic; fs_clk_i : in std_logic;
fmc_adc_core_ctl_fsm_cmd_o : out std_logic_vector(1 downto 0); fmc_adc_core_ctl_fsm_cmd_o : out std_logic_vector(1 downto 0);
fmc_adc_core_ctl_fsm_cmd_wr_o : out std_logic; fmc_adc_core_ctl_fsm_cmd_wr_o : out std_logic;
...@@ -637,15 +638,16 @@ begin ...@@ -637,15 +638,16 @@ begin
cmp_fmc_adc_100Ms_csr : fmc_adc_100Ms_csr cmp_fmc_adc_100Ms_csr : fmc_adc_100Ms_csr
port map( port map(
rst_n_i => sys_rst_n_i, rst_n_i => sys_rst_n_i,
wb_clk_i => sys_clk_i, clk_sys_i => sys_clk_i,
wb_addr_i => wb_csr_adr_i, wb_adr_i => wb_csr_adr_i,
wb_data_i => wb_csr_dat_i, wb_dat_i => wb_csr_dat_i,
wb_data_o => wb_csr_dat_o, wb_dat_o => wb_csr_dat_o,
wb_cyc_i => wb_csr_cyc_i, wb_cyc_i => wb_csr_cyc_i,
wb_sel_i => wb_csr_sel_i, wb_sel_i => wb_csr_sel_i,
wb_stb_i => wb_csr_stb_i, wb_stb_i => wb_csr_stb_i,
wb_we_i => wb_csr_we_i, wb_we_i => wb_csr_we_i,
wb_ack_o => wb_csr_ack_o, wb_ack_o => wb_csr_ack_o,
wb_stall_o => open,
fs_clk_i => fs_clk, fs_clk_i => fs_clk,
fmc_adc_core_ctl_fsm_cmd_o => fsm_cmd, fmc_adc_core_ctl_fsm_cmd_o => fsm_cmd,
fmc_adc_core_ctl_fsm_cmd_wr_o => fsm_cmd_wr, fmc_adc_core_ctl_fsm_cmd_wr_o => fsm_cmd_wr,
......
hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
View file @ b4cf7521
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hdl/spec/rtl/carrier_csr.vhd
View file @ b4cf7521
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd -- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb -- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Mon Mar 11 17:11:09 2013 -- Created : Tue Apr 9 18:41:24 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...@@ -17,15 +17,16 @@ use ieee.numeric_std.all; ...@@ -17,15 +17,16 @@ use ieee.numeric_std.all;
entity carrier_csr is entity carrier_csr is
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
wb_clk_i : in std_logic; clk_sys_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0); wb_adr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic; wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0); wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic; wb_stb_i : in std_logic;
wb_we_i : in std_logic; wb_we_i : in std_logic;
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'PCB revision' in reg: 'Carrier type and PCB version' -- Port for std_logic_vector field: 'PCB revision' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_pcb_rev_i : in std_logic_vector(3 downto 0); carrier_csr_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Reserved register' in reg: 'Carrier type and PCB version' -- Port for std_logic_vector field: 'Reserved register' in reg: 'Carrier type and PCB version'
...@@ -67,22 +68,20 @@ signal rwaddr_reg : std_logic_vector(1 downto 0); ...@@ -67,22 +68,20 @@ signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ; signal ack_in_progress : std_logic ;
signal wr_int : std_logic ; signal wr_int : std_logic ;
signal rd_int : std_logic ; signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0); signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0); signal allzeros : std_logic_vector(31 downto 0);
begin begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards. -- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i; wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i; bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i)); rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i); wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1'); allones <= (others => '1');
allzeros <= (others => '0'); allzeros <= (others => '0');
-- --
-- Main register bank access process. -- Main register bank access process.
process (bus_clock_int, rst_n_i) process (clk_sys_i, rst_n_i)
begin begin
if (rst_n_i = '0') then if (rst_n_i = '0') then
ack_sreg <= "0000000000"; ack_sreg <= "0000000000";
...@@ -92,7 +91,7 @@ begin ...@@ -92,7 +91,7 @@ begin
carrier_csr_ctrl_led_red_int <= '0'; carrier_csr_ctrl_led_red_int <= '0';
carrier_csr_ctrl_dac_clr_n_int <= '0'; carrier_csr_ctrl_dac_clr_n_int <= '0';
carrier_csr_ctrl_reserved_int <= "00000000000000000000000000000"; carrier_csr_ctrl_reserved_int <= "00000000000000000000000000000";
elsif rising_edge(bus_clock_int) then elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register -- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1); ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0'; ack_sreg(9) <= '0';
...@@ -106,43 +105,33 @@ begin ...@@ -106,43 +105,33 @@ begin
case rwaddr_reg(1 downto 0) is case rwaddr_reg(1 downto 0) is
when "00" => when "00" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
else
rddata_reg(3 downto 0) <= carrier_csr_carrier_pcb_rev_i;
rddata_reg(15 downto 4) <= carrier_csr_carrier_reserved_i;
rddata_reg(31 downto 16) <= carrier_csr_carrier_type_i;
end if; end if;
rddata_reg(3 downto 0) <= carrier_csr_carrier_pcb_rev_i;
rddata_reg(15 downto 4) <= carrier_csr_carrier_reserved_i;
rddata_reg(31 downto 16) <= carrier_csr_carrier_type_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01" => when "01" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
else
rddata_reg(0) <= carrier_csr_stat_fmc_pres_i;
rddata_reg(1) <= carrier_csr_stat_p2l_pll_lck_i;
rddata_reg(2) <= carrier_csr_stat_sys_pll_lck_i;
rddata_reg(3) <= carrier_csr_stat_ddr3_cal_done_i;
rddata_reg(31 downto 4) <= carrier_csr_stat_reserved_i;
end if; end if;
rddata_reg(0) <= carrier_csr_stat_fmc_pres_i;
rddata_reg(1) <= carrier_csr_stat_p2l_pll_lck_i;
rddata_reg(2) <= carrier_csr_stat_sys_pll_lck_i;
rddata_reg(3) <= carrier_csr_stat_ddr3_cal_done_i;
rddata_reg(31 downto 4) <= carrier_csr_stat_reserved_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "10" => when "10" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
carrier_csr_ctrl_led_green_int <= wrdata_reg(0); carrier_csr_ctrl_led_green_int <= wrdata_reg(0);
rddata_reg(1) <= 'X';
carrier_csr_ctrl_led_red_int <= wrdata_reg(1); carrier_csr_ctrl_led_red_int <= wrdata_reg(1);
rddata_reg(2) <= 'X';
carrier_csr_ctrl_dac_clr_n_int <= wrdata_reg(2); carrier_csr_ctrl_dac_clr_n_int <= wrdata_reg(2);
carrier_csr_ctrl_reserved_int <= wrdata_reg(31 downto 3); carrier_csr_ctrl_reserved_int <= wrdata_reg(31 downto 3);
else
rddata_reg(0) <= carrier_csr_ctrl_led_green_int;
rddata_reg(1) <= carrier_csr_ctrl_led_red_int;
rddata_reg(2) <= carrier_csr_ctrl_dac_clr_n_int;
rddata_reg(31 downto 3) <= carrier_csr_ctrl_reserved_int;
end if; end if;
rddata_reg(0) <= carrier_csr_ctrl_led_green_int;
rddata_reg(1) <= carrier_csr_ctrl_led_red_int;
rddata_reg(2) <= carrier_csr_ctrl_dac_clr_n_int;
rddata_reg(31 downto 3) <= carrier_csr_ctrl_reserved_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when others => when others =>
...@@ -157,7 +146,7 @@ begin ...@@ -157,7 +146,7 @@ begin
-- Drive the data output bus -- Drive the data output bus
wb_data_o <= rddata_reg; wb_dat_o <= rddata_reg;
-- PCB revision -- PCB revision
-- Reserved register -- Reserved register
-- Carrier type -- Carrier type
...@@ -174,7 +163,8 @@ begin ...@@ -174,7 +163,8 @@ begin
carrier_csr_ctrl_dac_clr_n_o <= carrier_csr_ctrl_dac_clr_n_int; carrier_csr_ctrl_dac_clr_n_o <= carrier_csr_ctrl_dac_clr_n_int;
-- Reserved -- Reserved
carrier_csr_ctrl_reserved_o <= carrier_csr_ctrl_reserved_int; carrier_csr_ctrl_reserved_o <= carrier_csr_ctrl_reserved_int;
rwaddr_reg <= wb_addr_i; rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter. -- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0); wb_ack_o <= ack_sreg(0);
end syn; end syn;
hdl/spec/rtl/irq_controller.vhd
View file @ b4cf7521
...@@ -77,15 +77,16 @@ architecture rtl of irq_controller is ...@@ -77,15 +77,16 @@ architecture rtl of irq_controller is
component irq_controller_regs component irq_controller_regs
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
wb_clk_i : in std_logic; clk_sys_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0); wb_adr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic; wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0); wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic; wb_stb_i : in std_logic;
wb_we_i : in std_logic; wb_we_i : in std_logic;
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
irq_ctrl_multi_irq_o : out std_logic_vector(31 downto 0); irq_ctrl_multi_irq_o : out std_logic_vector(31 downto 0);
irq_ctrl_multi_irq_i : in std_logic_vector(31 downto 0); irq_ctrl_multi_irq_i : in std_logic_vector(31 downto 0);
irq_ctrl_multi_irq_load_o : out std_logic; irq_ctrl_multi_irq_load_o : out std_logic;
...@@ -119,15 +120,16 @@ begin ...@@ -119,15 +120,16 @@ begin
cmp_irq_controller_regs : irq_controller_regs cmp_irq_controller_regs : irq_controller_regs
port map( port map(
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
wb_clk_i => clk_i, clk_sys_i => clk_i,
wb_addr_i => wb_adr_i, wb_adr_i => wb_adr_i,
wb_data_i => wb_dat_i, wb_dat_i => wb_dat_i,
wb_data_o => wb_dat_o, wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i, wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i, wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i, wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i, wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o, wb_ack_o => wb_ack_o,
wb_stall_o => open,
irq_ctrl_multi_irq_o => multi_irq_rst, irq_ctrl_multi_irq_o => multi_irq_rst,
irq_ctrl_multi_irq_load_o => multi_irq_rst_en, irq_ctrl_multi_irq_load_o => multi_irq_rst_en,
irq_ctrl_multi_irq_i => multi_irq, irq_ctrl_multi_irq_i => multi_irq,
......
hdl/spec/rtl/irq_controller_regs.vhd
View file @ b4cf7521
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : ../rtl/irq_controller_regs.vhd -- File : ../rtl/irq_controller_regs.vhd
-- Author : auto-generated by wbgen2 from irq_controller_regs.wb -- Author : auto-generated by wbgen2 from irq_controller_regs.wb
-- Created : Wed Jan 18 09:43:55 2012 -- Created : Tue Apr 9 18:41:31 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb
...@@ -17,15 +17,16 @@ use ieee.numeric_std.all; ...@@ -17,15 +17,16 @@ use ieee.numeric_std.all;
entity irq_controller_regs is entity irq_controller_regs is
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
wb_clk_i : in std_logic; clk_sys_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0); wb_adr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic; wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0); wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic; wb_stb_i : in std_logic;
wb_we_i : in std_logic; wb_we_i : in std_logic;
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'Multiple interrupt' in reg: 'Multiple interrupt register' -- Port for std_logic_vector field: 'Multiple interrupt' in reg: 'Multiple interrupt register'
irq_ctrl_multi_irq_o : out std_logic_vector(31 downto 0); irq_ctrl_multi_irq_o : out std_logic_vector(31 downto 0);
irq_ctrl_multi_irq_i : in std_logic_vector(31 downto 0); irq_ctrl_multi_irq_i : in std_logic_vector(31 downto 0);
...@@ -50,22 +51,20 @@ signal rwaddr_reg : std_logic_vector(1 downto 0); ...@@ -50,22 +51,20 @@ signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ; signal ack_in_progress : std_logic ;
signal wr_int : std_logic ; signal wr_int : std_logic ;
signal rd_int : std_logic ; signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0); signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0); signal allzeros : std_logic_vector(31 downto 0);
begin begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards. -- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i; wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i; bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i)); rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i); wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1'); allones <= (others => '1');
allzeros <= (others => '0'); allzeros <= (others => '0');
-- --
-- Main register bank access process. -- Main register bank access process.
process (bus_clock_int, rst_n_i) process (clk_sys_i, rst_n_i)
begin begin
if (rst_n_i = '0') then if (rst_n_i = '0') then
ack_sreg <= "0000000000"; ack_sreg <= "0000000000";
...@@ -74,7 +73,7 @@ begin ...@@ -74,7 +73,7 @@ begin
irq_ctrl_multi_irq_load_o <= '0'; irq_ctrl_multi_irq_load_o <= '0';
irq_ctrl_src_load_o <= '0'; irq_ctrl_src_load_o <= '0';
irq_ctrl_en_mask_int <= "00000000000000000000000000000000"; irq_ctrl_en_mask_int <= "00000000000000000000000000000000";
elsif rising_edge(bus_clock_int) then elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register -- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1); ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0'; ack_sreg(9) <= '0';
...@@ -93,25 +92,22 @@ begin ...@@ -93,25 +92,22 @@ begin
when "00" => when "00" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
irq_ctrl_multi_irq_load_o <= '1'; irq_ctrl_multi_irq_load_o <= '1';
else
rddata_reg(31 downto 0) <= irq_ctrl_multi_irq_i;
end if; end if;
rddata_reg(31 downto 0) <= irq_ctrl_multi_irq_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01" => when "01" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
irq_ctrl_src_load_o <= '1'; irq_ctrl_src_load_o <= '1';
else
rddata_reg(31 downto 0) <= irq_ctrl_src_i;
end if; end if;
rddata_reg(31 downto 0) <= irq_ctrl_src_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "10" => when "10" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
irq_ctrl_en_mask_int <= wrdata_reg(31 downto 0); irq_ctrl_en_mask_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= irq_ctrl_en_mask_int;
end if; end if;
rddata_reg(31 downto 0) <= irq_ctrl_en_mask_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when others => when others =>
...@@ -126,14 +122,15 @@ begin ...@@ -126,14 +122,15 @@ begin
-- Drive the data output bus -- Drive the data output bus
wb_data_o <= rddata_reg; wb_dat_o <= rddata_reg;
-- Multiple interrupt -- Multiple interrupt
irq_ctrl_multi_irq_o <= wrdata_reg(31 downto 0); irq_ctrl_multi_irq_o <= wrdata_reg(31 downto 0);
-- Interrupt sources -- Interrupt sources
irq_ctrl_src_o <= wrdata_reg(31 downto 0); irq_ctrl_src_o <= wrdata_reg(31 downto 0);
-- Interrupt enable mask -- Interrupt enable mask
irq_ctrl_en_mask_o <= irq_ctrl_en_mask_int; irq_ctrl_en_mask_o <= irq_ctrl_en_mask_int;
rwaddr_reg <= wb_addr_i; rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter. -- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0); wb_ack_o <= ack_sreg(0);
end syn; end syn;
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ b4cf7521
...@@ -172,15 +172,16 @@ architecture rtl of spec_top_fmc_adc_100Ms is ...@@ -172,15 +172,16 @@ architecture rtl of spec_top_fmc_adc_100Ms is
component carrier_csr component carrier_csr
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
wb_clk_i : in std_logic; clk_sys_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0); wb_adr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic; wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0); wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic; wb_stb_i : in std_logic;
wb_we_i : in std_logic; wb_we_i : in std_logic;
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
carrier_csr_carrier_pcb_rev_i : in std_logic_vector(3 downto 0); carrier_csr_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
carrier_csr_carrier_reserved_i : in std_logic_vector(11 downto 0); carrier_csr_carrier_reserved_i : in std_logic_vector(11 downto 0);
carrier_csr_carrier_type_i : in std_logic_vector(15 downto 0); carrier_csr_carrier_type_i : in std_logic_vector(15 downto 0);
...@@ -782,15 +783,16 @@ begin ...@@ -782,15 +783,16 @@ begin
cmp_carrier_csr : carrier_csr cmp_carrier_csr : carrier_csr
port map( port map(
rst_n_i => sys_rst_n, rst_n_i => sys_rst_n,
wb_clk_i => sys_clk_125, clk_sys_i => sys_clk_125,
wb_addr_i => cnx_master_out(c_SLAVE_SPEC_CSR).adr(3 downto 2), -- cnx_master_out.adr is byte address wb_adr_i => cnx_master_out(c_SLAVE_SPEC_CSR).adr(3 downto 2), -- cnx_master_out.adr is byte address
wb_data_i => cnx_master_out(c_SLAVE_SPEC_CSR).dat, wb_dat_i => cnx_master_out(c_SLAVE_SPEC_CSR).dat,
wb_data_o => cnx_master_in(c_SLAVE_SPEC_CSR).dat, wb_dat_o => cnx_master_in(c_SLAVE_SPEC_CSR).dat,
wb_cyc_i => cnx_master_out(c_SLAVE_SPEC_CSR).cyc, wb_cyc_i => cnx_master_out(c_SLAVE_SPEC_CSR).cyc,
wb_sel_i => cnx_master_out(c_SLAVE_SPEC_CSR).sel, wb_sel_i => cnx_master_out(c_SLAVE_SPEC_CSR).sel,
wb_stb_i => cnx_master_out(c_SLAVE_SPEC_CSR).stb, wb_stb_i => cnx_master_out(c_SLAVE_SPEC_CSR).stb,
wb_we_i => cnx_master_out(c_SLAVE_SPEC_CSR).we, wb_we_i => cnx_master_out(c_SLAVE_SPEC_CSR).we,
wb_ack_o => cnx_master_in(c_SLAVE_SPEC_CSR).ack, wb_ack_o => cnx_master_in(c_SLAVE_SPEC_CSR).ack,
wb_stall_o => open,
carrier_csr_carrier_pcb_rev_i => pcb_ver_i, carrier_csr_carrier_pcb_rev_i => pcb_ver_i,
carrier_csr_carrier_reserved_i => X"000", carrier_csr_carrier_reserved_i => X"000",
carrier_csr_carrier_type_i => c_CARRIER_TYPE, carrier_csr_carrier_type_i => c_CARRIER_TYPE,
......
hdl/spec/rtl/utc_core.vhd
View file @ b4cf7521
...@@ -78,15 +78,16 @@ architecture rtl of utc_core is ...@@ -78,15 +78,16 @@ architecture rtl of utc_core is
component utc_core_regs component utc_core_regs
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
wb_clk_i : in std_logic; clk_sys_i : in std_logic;
wb_addr_i : in std_logic_vector(4 downto 0); wb_adr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic; wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0); wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic; wb_stb_i : in std_logic;
wb_we_i : in std_logic; wb_we_i : in std_logic;
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
utc_core_seconds_o : out std_logic_vector(31 downto 0); utc_core_seconds_o : out std_logic_vector(31 downto 0);
utc_core_seconds_i : in std_logic_vector(31 downto 0); utc_core_seconds_i : in std_logic_vector(31 downto 0);
utc_core_seconds_load_o : out std_logic; utc_core_seconds_load_o : out std_logic;
...@@ -152,15 +153,16 @@ begin ...@@ -152,15 +153,16 @@ begin
cmp_utc_core_regs : utc_core_regs cmp_utc_core_regs : utc_core_regs
port map( port map(
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
wb_clk_i => clk_i, clk_sys_i => clk_i,
wb_addr_i => wb_adr_i, wb_adr_i => wb_adr_i,
wb_data_i => wb_dat_i, wb_dat_i => wb_dat_i,
wb_data_o => wb_dat_o, wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i, wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i, wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i, wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i, wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o, wb_ack_o => wb_ack_o,
wb_stall_o => open,
utc_core_seconds_o => utc_seconds_load_value, utc_core_seconds_o => utc_seconds_load_value,
utc_core_seconds_i => utc_seconds, utc_core_seconds_i => utc_seconds,
utc_core_seconds_load_o => utc_seconds_load_en, utc_core_seconds_load_o => utc_seconds_load_en,
......
hdl/spec/rtl/utc_core_regs.vhd
View file @ b4cf7521
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : ../rtl/utc_core_regs.vhd -- File : ../rtl/utc_core_regs.vhd
-- Author : auto-generated by wbgen2 from utc_core_regs.wb -- Author : auto-generated by wbgen2 from utc_core_regs.wb
-- Created : Tue Nov 22 10:20:36 2011 -- Created : Tue Apr 9 18:41:27 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE utc_core_regs.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE utc_core_regs.wb
...@@ -17,15 +17,16 @@ use ieee.numeric_std.all; ...@@ -17,15 +17,16 @@ use ieee.numeric_std.all;
entity utc_core_regs is entity utc_core_regs is
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
wb_clk_i : in std_logic; clk_sys_i : in std_logic;
wb_addr_i : in std_logic_vector(4 downto 0); wb_adr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic; wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0); wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic; wb_stb_i : in std_logic;
wb_we_i : in std_logic; wb_we_i : in std_logic;
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'UTC seconds' in reg: 'UTC seconds register' -- Port for std_logic_vector field: 'UTC seconds' in reg: 'UTC seconds register'
utc_core_seconds_o : out std_logic_vector(31 downto 0); utc_core_seconds_o : out std_logic_vector(31 downto 0);
utc_core_seconds_i : in std_logic_vector(31 downto 0); utc_core_seconds_i : in std_logic_vector(31 downto 0);
...@@ -79,22 +80,20 @@ signal rwaddr_reg : std_logic_vector(4 downto 0); ...@@ -79,22 +80,20 @@ signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ; signal ack_in_progress : std_logic ;
signal wr_int : std_logic ; signal wr_int : std_logic ;
signal rd_int : std_logic ; signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0); signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0); signal allzeros : std_logic_vector(31 downto 0);
begin begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards. -- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i; wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i; bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i)); rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i); wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1'); allones <= (others => '1');
allzeros <= (others => '0'); allzeros <= (others => '0');
-- --
-- Main register bank access process. -- Main register bank access process.
process (bus_clock_int, rst_n_i) process (clk_sys_i, rst_n_i)
begin begin
if (rst_n_i = '0') then if (rst_n_i = '0') then
ack_sreg <= "0000000000"; ack_sreg <= "0000000000";
...@@ -102,7 +101,7 @@ begin ...@@ -102,7 +101,7 @@ begin
rddata_reg <= "00000000000000000000000000000000"; rddata_reg <= "00000000000000000000000000000000";
utc_core_seconds_load_o <= '0'; utc_core_seconds_load_o <= '0';
utc_core_coarse_load_o <= '0'; utc_core_coarse_load_o <= '0';
elsif rising_edge(bus_clock_int) then elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register -- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1); ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0'; ack_sreg(9) <= '0';
...@@ -121,129 +120,111 @@ begin ...@@ -121,129 +120,111 @@ begin
when "00000" => when "00000" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
utc_core_seconds_load_o <= '1'; utc_core_seconds_load_o <= '1';
else
rddata_reg(31 downto 0) <= utc_core_seconds_i;
end if; end if;
rddata_reg(31 downto 0) <= utc_core_seconds_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00001" => when "00001" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
utc_core_coarse_load_o <= '1'; utc_core_coarse_load_o <= '1';
else
rddata_reg(31 downto 0) <= utc_core_coarse_i;
end if; end if;
rddata_reg(31 downto 0) <= utc_core_coarse_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00010" => when "00010" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_meta_i;
end if; end if;
rddata_reg(31 downto 0) <= utc_core_trig_tag_meta_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00011" => when "00011" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_seconds_i;
end if; end if;
rddata_reg(31 downto 0) <= utc_core_trig_tag_seconds_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00100" => when "00100" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_coarse_i;
end if; end if;
rddata_reg(31 downto 0) <= utc_core_trig_tag_coarse_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00101" => when "00101" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_fine_i;
end if; end if;
rddata_reg(31 downto 0) <= utc_core_trig_tag_fine_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00110" => when "00110" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_meta_i;
end if; end if;
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_meta_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00111" => when "00111" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_seconds_i;
end if; end if;
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_seconds_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01000" => when "01000" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_coarse_i;
end if; end if;
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_coarse_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01001" => when "01001" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_fine_i;
end if; end if;
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_fine_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01010" => when "01010" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_meta_i;
end if; end if;
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_meta_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01011" => when "01011" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_seconds_i;
end if; end if;
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_seconds_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01100" => when "01100" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_coarse_i;
end if; end if;
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_coarse_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01101" => when "01101" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_fine_i;
end if; end if;
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_fine_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01110" => when "01110" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_meta_i;
end if; end if;
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_meta_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01111" => when "01111" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_seconds_i;
end if; end if;
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_seconds_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "10000" => when "10000" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_coarse_i;
end if; end if;
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_coarse_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "10001" => when "10001" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_fine_i;
end if; end if;
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_fine_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when others => when others =>
...@@ -258,7 +239,7 @@ begin ...@@ -258,7 +239,7 @@ begin
-- Drive the data output bus -- Drive the data output bus
wb_data_o <= rddata_reg; wb_dat_o <= rddata_reg;
-- UTC seconds -- UTC seconds
utc_core_seconds_o <= wrdata_reg(31 downto 0); utc_core_seconds_o <= wrdata_reg(31 downto 0);
-- UTC coarse time -- UTC coarse time
...@@ -279,7 +260,8 @@ begin ...@@ -279,7 +260,8 @@ begin
-- Acquisition end time-tag UTC seconds -- Acquisition end time-tag UTC seconds
-- Acquisition end time-tag coarse time -- Acquisition end time-tag coarse time
-- Acquisition end time-tag fine time -- Acquisition end time-tag fine time
rwaddr_reg <= wb_addr_i; rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter. -- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0); wb_ack_o <= ack_sreg(0);
end syn; end syn;
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