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FMC ADC 100M 14b 4cha - Gateware
Commits
b48832a9
Commit
b48832a9
authored
Dec 13, 2013
by
Matthieu Cattin
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hdl: Insert trigger time-tag in data, after post-trigger samples.
parent
94774b66
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7 changed files
with
385 additions
and
311 deletions
+385
-311
fmc_adc_100Ms_core.vhd
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
+290
-241
fmc_adc_100Ms_core_pkg.vhd
hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
+6
-1
fmc_adc_mezzanine.vhd
hdl/adc/rtl/fmc_adc_mezzanine.vhd
+10
-4
fmc_adc_mezzanine_pkg.vhd
hdl/adc/rtl/fmc_adc_mezzanine_pkg.vhd
+5
-0
timetag_core.vhd
hdl/ip_cores/timetag_core/rtl/timetag_core.vhd
+57
-65
timetag_core_pkg.vhd
hdl/ip_cores/timetag_core/rtl/timetag_core_pkg.vhd
+12
-0
spec_top_fmc_adc_100Ms.vhd
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
+5
-0
No files found.
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @
b48832a9
This diff is collapsed.
Click to expand it.
hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
View file @
b48832a9
...
...
@@ -37,6 +37,8 @@
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
all
;
use
IEEE
.
NUMERIC_STD
.
all
;
use
work
.
timetag_core_pkg
.
all
;
package
fmc_adc_100Ms_core_pkg
is
...
...
@@ -51,7 +53,7 @@ package fmc_adc_100Ms_core_pkg is
component
fmc_adc_100Ms_core
generic
(
g_multishot_ram_size
:
natural
:
=
2048
;
g_carrier_type
:
string
:
=
"SPEC"
g_carrier_type
:
string
:
=
"SPEC"
);
port
(
-- Clock, reset
...
...
@@ -85,6 +87,9 @@ package fmc_adc_100Ms_core_pkg is
acq_stop_p_o
:
out
std_logic
;
acq_end_p_o
:
out
std_logic
;
-- Trigger time-tag input
trigger_tag_i
:
t_timetag
;
-- FMC interface
ext_trigger_p_i
:
in
std_logic
;
-- External trigger
ext_trigger_n_i
:
in
std_logic
;
...
...
hdl/adc/rtl/fmc_adc_mezzanine.vhd
View file @
b48832a9
...
...
@@ -43,12 +43,13 @@ use IEEE.NUMERIC_STD.all;
library
work
;
use
work
.
fmc_adc_100Ms_core_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
timetag_core_pkg
.
all
;
entity
fmc_adc_mezzanine
is
generic
(
g_multishot_ram_size
:
natural
:
=
2048
;
g_carrier_type
:
string
:
=
"SPEC"
g_carrier_type
:
string
:
=
"SPEC"
);
port
(
-- Clock, reset
...
...
@@ -83,6 +84,9 @@ entity fmc_adc_mezzanine is
acq_stop_p_o
:
out
std_logic
;
acq_end_p_o
:
out
std_logic
;
-- Trigger time-tag input
trigger_tag_i
:
t_timetag
;
-- FMC interface
ext_trigger_p_i
:
in
std_logic
;
-- External trigger
ext_trigger_n_i
:
in
std_logic
;
...
...
@@ -213,8 +217,8 @@ architecture rtl of fmc_adc_mezzanine is
signal
si570_sda_oe_n
:
std_logic
;
-- Mezzanine 1-wire
signal
mezz_owr_en
:
std_logic_vector
(
0
downto
0
);
signal
mezz_owr_i
:
std_logic_vector
(
0
downto
0
);
signal
mezz_owr_en
:
std_logic_vector
(
0
downto
0
);
signal
mezz_owr_i
:
std_logic_vector
(
0
downto
0
);
begin
...
...
@@ -369,7 +373,7 @@ begin
cmp_fmc_adc_100Ms_core
:
fmc_adc_100Ms_core
generic
map
(
g_multishot_ram_size
=>
g_multishot_ram_size
,
g_carrier_type
=>
g_carrier_type
g_carrier_type
=>
g_carrier_type
)
port
map
(
sys_clk_i
=>
sys_clk_i
,
...
...
@@ -399,6 +403,8 @@ begin
acq_stop_p_o
=>
acq_stop_p_o
,
acq_end_p_o
=>
acq_end_p_o
,
trigger_tag_i
=>
trigger_tag_i
,
ext_trigger_p_i
=>
ext_trigger_p_i
,
ext_trigger_n_i
=>
ext_trigger_n_i
,
...
...
hdl/adc/rtl/fmc_adc_mezzanine_pkg.vhd
View file @
b48832a9
...
...
@@ -37,6 +37,8 @@
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
all
;
use
IEEE
.
NUMERIC_STD
.
all
;
use
work
.
timetag_core_pkg
.
all
;
package
fmc_adc_mezzanine_pkg
is
...
...
@@ -86,6 +88,9 @@ package fmc_adc_mezzanine_pkg is
acq_stop_p_o
:
out
std_logic
;
acq_end_p_o
:
out
std_logic
;
-- Trigger time-tag input
trigger_tag_i
:
t_timetag
;
-- FMC interface
ext_trigger_p_i
:
in
std_logic
;
-- External trigger
ext_trigger_n_i
:
in
std_logic
;
...
...
hdl/ip_cores/timetag_core/rtl/timetag_core.vhd
View file @
b48832a9
...
...
@@ -38,7 +38,7 @@
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
all
;
use
IEEE
.
NUMERIC_STD
.
all
;
use
work
.
timetag_core_pkg
.
all
;
--library UNISIM;
--use UNISIM.vcomponents.all;
...
...
@@ -56,6 +56,9 @@ entity timetag_core is
acq_stop_p_i
:
in
std_logic
;
acq_end_p_i
:
in
std_logic
;
-- Trigger time-tag output
trig_tag_o
:
out
t_timetag
;
-- Wishbone interface
wb_adr_i
:
in
std_logic_vector
(
4
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
...
...
@@ -116,30 +119,18 @@ architecture rtl of timetag_core is
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal
timetag_seconds
:
std_logic_vector
(
31
downto
0
);
signal
timetag_seconds_cnt
:
unsigned
(
31
downto
0
);
signal
timetag_seconds_load_value
:
std_logic_vector
(
31
downto
0
);
signal
timetag_seconds_load_en
:
std_logic
;
signal
timetag_coarse
:
std_logic_vector
(
31
downto
0
);
signal
timetag_coarse_cnt
:
unsigned
(
31
downto
0
);
signal
timetag_coarse_load_value
:
std_logic_vector
(
31
downto
0
);
signal
timetag_coarse_load_en
:
std_logic
;
signal
timetag_trig_tag_meta
:
std_logic_vector
(
31
downto
0
);
signal
timetag_trig_tag_seconds
:
std_logic_vector
(
31
downto
0
);
signal
timetag_trig_tag_coarse
:
std_logic_vector
(
31
downto
0
);
signal
timetag_trig_tag_fine
:
std_logic_vector
(
31
downto
0
);
signal
timetag_acq_start_tag_meta
:
std_logic_vector
(
31
downto
0
);
signal
timetag_acq_start_tag_seconds
:
std_logic_vector
(
31
downto
0
);
signal
timetag_acq_start_tag_coarse
:
std_logic_vector
(
31
downto
0
);
signal
timetag_acq_start_tag_fine
:
std_logic_vector
(
31
downto
0
);
signal
timetag_acq_stop_tag_meta
:
std_logic_vector
(
31
downto
0
);
signal
timetag_acq_stop_tag_seconds
:
std_logic_vector
(
31
downto
0
);
signal
timetag_acq_stop_tag_coarse
:
std_logic_vector
(
31
downto
0
);
signal
timetag_acq_stop_tag_fine
:
std_logic_vector
(
31
downto
0
);
signal
timetag_acq_end_tag_meta
:
std_logic_vector
(
31
downto
0
);
signal
timetag_acq_end_tag_seconds
:
std_logic_vector
(
31
downto
0
);
signal
timetag_acq_end_tag_coarse
:
std_logic_vector
(
31
downto
0
);
signal
timetag_acq_end_tag_fine
:
std_logic_vector
(
31
downto
0
);
signal
timetag_seconds
:
std_logic_vector
(
31
downto
0
);
signal
timetag_seconds_cnt
:
unsigned
(
31
downto
0
);
signal
timetag_seconds_load_value
:
std_logic_vector
(
31
downto
0
);
signal
timetag_seconds_load_en
:
std_logic
;
signal
timetag_coarse
:
std_logic_vector
(
31
downto
0
);
signal
timetag_coarse_cnt
:
unsigned
(
31
downto
0
);
signal
timetag_coarse_load_value
:
std_logic_vector
(
31
downto
0
);
signal
timetag_coarse_load_en
:
std_logic
;
signal
trig_tag
:
t_timetag
;
signal
acq_start_tag
:
t_timetag
;
signal
acq_stop_tag
:
t_timetag
;
signal
acq_end_tag
:
t_timetag
;
signal
local_pps
:
std_logic
;
...
...
@@ -169,22 +160,22 @@ begin
timetag_core_coarse_o
=>
timetag_coarse_load_value
,
timetag_core_coarse_i
=>
timetag_coarse
,
timetag_core_coarse_load_o
=>
timetag_coarse_load_en
,
timetag_core_trig_tag_meta_i
=>
t
imetag_trig_tag_
meta
,
timetag_core_trig_tag_seconds_i
=>
t
imetag_trig_tag_
seconds
,
timetag_core_trig_tag_coarse_i
=>
t
imetag_trig_tag_
coarse
,
timetag_core_trig_tag_fine_i
=>
t
imetag_trig_tag_
fine
,
timetag_core_acq_start_tag_meta_i
=>
timetag_acq_start_tag_
meta
,
timetag_core_acq_start_tag_seconds_i
=>
timetag_acq_start_tag_
seconds
,
timetag_core_acq_start_tag_coarse_i
=>
timetag_acq_start_tag_
coarse
,
timetag_core_acq_start_tag_fine_i
=>
timetag_acq_start_tag_
fine
,
timetag_core_acq_stop_tag_meta_i
=>
timetag_acq_stop_tag_
meta
,
timetag_core_acq_stop_tag_seconds_i
=>
timetag_acq_stop_tag_
seconds
,
timetag_core_acq_stop_tag_coarse_i
=>
timetag_acq_stop_tag_
coarse
,
timetag_core_acq_stop_tag_fine_i
=>
timetag_acq_stop_tag_
fine
,
timetag_core_acq_end_tag_meta_i
=>
timetag_acq_end_tag_
meta
,
timetag_core_acq_end_tag_seconds_i
=>
timetag_acq_end_tag_
seconds
,
timetag_core_acq_end_tag_coarse_i
=>
timetag_acq_end_tag_
coarse
,
timetag_core_acq_end_tag_fine_i
=>
timetag_acq_end_tag_
fine
timetag_core_trig_tag_meta_i
=>
t
rig_tag
.
meta
,
timetag_core_trig_tag_seconds_i
=>
t
rig_tag
.
seconds
,
timetag_core_trig_tag_coarse_i
=>
t
rig_tag
.
coarse
,
timetag_core_trig_tag_fine_i
=>
t
rig_tag
.
fine
,
timetag_core_acq_start_tag_meta_i
=>
acq_start_tag
.
meta
,
timetag_core_acq_start_tag_seconds_i
=>
acq_start_tag
.
seconds
,
timetag_core_acq_start_tag_coarse_i
=>
acq_start_tag
.
coarse
,
timetag_core_acq_start_tag_fine_i
=>
acq_start_tag
.
fine
,
timetag_core_acq_stop_tag_meta_i
=>
acq_stop_tag
.
meta
,
timetag_core_acq_stop_tag_seconds_i
=>
acq_stop_tag
.
seconds
,
timetag_core_acq_stop_tag_coarse_i
=>
acq_stop_tag
.
coarse
,
timetag_core_acq_stop_tag_fine_i
=>
acq_stop_tag
.
fine
,
timetag_core_acq_end_tag_meta_i
=>
acq_end_tag
.
meta
,
timetag_core_acq_end_tag_seconds_i
=>
acq_end_tag
.
seconds
,
timetag_core_acq_end_tag_coarse_i
=>
acq_end_tag
.
coarse
,
timetag_core_acq_end_tag_fine_i
=>
acq_end_tag
.
fine
);
------------------------------------------------------------------------------
...
...
@@ -236,17 +227,18 @@ begin
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
t
imetag_trig_tag_
seconds
<=
(
others
=>
'0'
);
t
imetag_trig_tag_
coarse
<=
(
others
=>
'0'
);
t
imetag_trig_tag_
fine
<=
(
others
=>
'0'
);
t
rig_tag
.
seconds
<=
(
others
=>
'0'
);
t
rig_tag
.
coarse
<=
(
others
=>
'0'
);
t
rig_tag
.
fine
<=
(
others
=>
'0'
);
elsif
trigger_p_i
=
'1'
then
t
imetag_trig_tag_
seconds
<=
timetag_seconds
;
t
imetag_trig_tag_
coarse
<=
timetag_coarse
;
t
rig_tag
.
seconds
<=
timetag_seconds
;
t
rig_tag
.
coarse
<=
timetag_coarse
;
end
if
;
end
if
;
end
process
p_trig_tag
;
timetag_trig_tag_meta
<=
X"00000000"
;
trig_tag
.
meta
<=
X"00000000"
;
trig_tag_o
<=
trig_tag
;
------------------------------------------------------------------------------
-- Last acquisition start event time-tag
...
...
@@ -255,17 +247,17 @@ begin
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
timetag_acq_start_tag_
seconds
<=
(
others
=>
'0'
);
timetag_acq_start_tag_
coarse
<=
(
others
=>
'0'
);
timetag_acq_start_tag_
fine
<=
(
others
=>
'0'
);
acq_start_tag
.
seconds
<=
(
others
=>
'0'
);
acq_start_tag
.
coarse
<=
(
others
=>
'0'
);
acq_start_tag
.
fine
<=
(
others
=>
'0'
);
elsif
acq_start_p_i
=
'1'
then
timetag_acq_start_tag_
seconds
<=
timetag_seconds
;
timetag_acq_start_tag_
coarse
<=
timetag_coarse
;
acq_start_tag
.
seconds
<=
timetag_seconds
;
acq_start_tag
.
coarse
<=
timetag_coarse
;
end
if
;
end
if
;
end
process
p_acq_start_tag
;
timetag_acq_start_tag_
meta
<=
X"00000000"
;
acq_start_tag
.
meta
<=
X"00000000"
;
------------------------------------------------------------------------------
-- Last acquisition stop event time-tag
...
...
@@ -274,17 +266,17 @@ begin
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
timetag_acq_stop_tag_
seconds
<=
(
others
=>
'0'
);
timetag_acq_stop_tag_
coarse
<=
(
others
=>
'0'
);
timetag_acq_stop_tag_
fine
<=
(
others
=>
'0'
);
acq_stop_tag
.
seconds
<=
(
others
=>
'0'
);
acq_stop_tag
.
coarse
<=
(
others
=>
'0'
);
acq_stop_tag
.
fine
<=
(
others
=>
'0'
);
elsif
acq_stop_p_i
=
'1'
then
timetag_acq_stop_tag_
seconds
<=
timetag_seconds
;
timetag_acq_stop_tag_
coarse
<=
timetag_coarse
;
acq_stop_tag
.
seconds
<=
timetag_seconds
;
acq_stop_tag
.
coarse
<=
timetag_coarse
;
end
if
;
end
if
;
end
process
p_acq_stop_tag
;
timetag_acq_stop_tag_
meta
<=
X"00000000"
;
acq_stop_tag
.
meta
<=
X"00000000"
;
------------------------------------------------------------------------------
-- Last acquisition end event time-tag
...
...
@@ -293,17 +285,17 @@ begin
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
timetag_acq_end_tag_
seconds
<=
(
others
=>
'0'
);
timetag_acq_end_tag_
coarse
<=
(
others
=>
'0'
);
timetag_acq_end_tag_
fine
<=
(
others
=>
'0'
);
acq_end_tag
.
seconds
<=
(
others
=>
'0'
);
acq_end_tag
.
coarse
<=
(
others
=>
'0'
);
acq_end_tag
.
fine
<=
(
others
=>
'0'
);
elsif
acq_end_p_i
=
'1'
then
timetag_acq_end_tag_
seconds
<=
timetag_seconds
;
timetag_acq_end_tag_
coarse
<=
timetag_coarse
;
acq_end_tag
.
seconds
<=
timetag_seconds
;
acq_end_tag
.
coarse
<=
timetag_coarse
;
end
if
;
end
if
;
end
process
p_acq_end_tag
;
timetag_acq_end_tag_
meta
<=
X"00000000"
;
acq_end_tag
.
meta
<=
X"00000000"
;
end
rtl
;
hdl/ip_cores/timetag_core/rtl/timetag_core_pkg.vhd
View file @
b48832a9
...
...
@@ -44,6 +44,15 @@ package timetag_core_pkg is
-- Constants declaration
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Types declaration
------------------------------------------------------------------------------
type
t_timetag
is
record
meta
:
std_logic_vector
(
31
downto
0
);
seconds
:
std_logic_vector
(
31
downto
0
);
coarse
:
std_logic_vector
(
31
downto
0
);
fine
:
std_logic_vector
(
31
downto
0
);
end
record
t_timetag
;
------------------------------------------------------------------------------
-- Components declaration
...
...
@@ -60,6 +69,9 @@ package timetag_core_pkg is
acq_stop_p_i
:
in
std_logic
;
acq_end_p_i
:
in
std_logic
;
-- Trigger time-tag output
trig_tag_o
:
out
t_timetag
;
-- Wishbone interface
wb_adr_i
:
in
std_logic_vector
(
4
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
...
...
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @
b48832a9
...
...
@@ -489,6 +489,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal
acq_start_p
:
std_logic
;
signal
acq_stop_p
:
std_logic
;
signal
acq_end_p
:
std_logic
;
signal
trigger_tag
:
t_timetag
;
-- led pwm
signal
led_pwm_update_cnt
:
unsigned
(
9
downto
0
);
...
...
@@ -795,6 +796,8 @@ begin
acq_stop_p_i
=>
acq_stop_p
,
acq_end_p_i
=>
acq_end_p
,
trig_tag_o
=>
trigger_tag
,
wb_adr_i
=>
cnx_master_out
(
c_WB_SLAVE_TIMETAG
)
.
adr
(
6
downto
2
),
-- cnx_master_out.adr is byte address
wb_dat_i
=>
cnx_master_out
(
c_WB_SLAVE_TIMETAG
)
.
dat
,
wb_dat_o
=>
cnx_master_in
(
c_WB_SLAVE_TIMETAG
)
.
dat
,
...
...
@@ -949,6 +952,8 @@ begin
acq_stop_p_o
=>
acq_stop_p
,
acq_end_p_o
=>
acq_end_p
,
trigger_tag_i
=>
trigger_tag
,
ext_trigger_p_i
=>
adc0_ext_trigger_p_i
,
ext_trigger_n_i
=>
adc0_ext_trigger_n_i
,
...
...
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