Commit ad1db4c2 authored by Matthieu Cattin's avatar Matthieu Cattin

syn: spec-fmc-adc gateware release 4.0

parent 5caab66f
...@@ -54,13 +54,13 @@ package sdb_meta_pkg is ...@@ -54,13 +54,13 @@ package sdb_meta_pkg is
syn_module_name => "spec_top_fmc_adc", syn_module_name => "spec_top_fmc_adc",
-- Commit ID (hex string, 128-bit = 32 char) -- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-32 -- git log -1 --format="%H" | cut -c1-32
syn_commit_id => "697546304b7a1890aba8d6effd935a0f", syn_commit_id => "26749f0a1873c215abb33942a8a335db",
-- Synthesis tool name (string, 8 char) -- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ", syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit) -- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000133", syn_tool_version => x"00000133",
-- Synthesis date (bcd encoded, 32-bit, yyyymmdd) -- Synthesis date (bcd encoded, 32-bit, yyyymmdd)
syn_date => x"20140116", syn_date => x"20140425",
-- Synthesised by (string, 15 char) -- Synthesised by (string, 15 char)
syn_username => "mcattin "); syn_username => "mcattin ");
...@@ -69,8 +69,8 @@ package sdb_meta_pkg is ...@@ -69,8 +69,8 @@ package sdb_meta_pkg is
product => ( product => (
vendor_id => x"000000000000CE42", -- CERN vendor_id => x"000000000000CE42", -- CERN
device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8 device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00030000", -- bcd encoded, [31:16] = major, [15:0] = minor version => x"00040000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20140116", -- yyyymmdd date => x"20140425", -- yyyymmdd
name => "spec_fmcadc100m14b ")); name => "spec_fmcadc100m14b "));
......
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...@@ -11,46 +11,46 @@ Target Device : xc6slx45t ...@@ -11,46 +11,46 @@ Target Device : xc6slx45t
Target Package : fgg484 Target Package : fgg484
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $ Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Thu Jan 16 17:57:07 2014 Mapped Date : Fri Apr 25 16:27:42 2014
Design Summary Design Summary
-------------- --------------
Number of errors: 0 Number of errors: 0
Number of warnings: 8 Number of warnings: 8
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 6,698 out of 54,576 12% Number of Slice Registers: 6,815 out of 54,576 12%
Number used as Flip Flops: 6,698 Number used as Flip Flops: 6,786
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 29
Number of Slice LUTs: 5,758 out of 27,288 21% Number of Slice LUTs: 6,024 out of 27,288 22%
Number used as logic: 5,404 out of 27,288 19% Number used as logic: 5,626 out of 27,288 20%
Number using O6 output only: 3,644 Number using O6 output only: 3,598
Number using O5 output only: 368 Number using O5 output only: 363
Number using O5 and O6: 1,392 Number using O5 and O6: 1,665
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1% Number used as Memory: 34 out of 6,408 1%
Number used as Dual Port RAM: 0 Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0 Number used as Single Port RAM: 0
Number used as Shift Register: 2 Number used as Shift Register: 34
Number using O6 output only: 2 Number using O6 output only: 2
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 32
Number used exclusively as route-thrus: 352 Number used exclusively as route-thrus: 364
Number with same-slice register load: 328 Number with same-slice register load: 340
Number with same-slice carry load: 24 Number with same-slice carry load: 24
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 2,468 out of 6,822 36% Number of occupied Slices: 2,500 out of 6,822 36%
Nummber of MUXCYs used: 1,440 out of 13,644 10% Nummber of MUXCYs used: 1,660 out of 13,644 12%
Number of LUT Flip Flop pairs used: 7,910 Number of LUT Flip Flop pairs used: 8,097
Number with an unused Flip Flop: 1,939 out of 7,910 24% Number with an unused Flip Flop: 2,095 out of 8,097 25%
Number with an unused LUT: 2,152 out of 7,910 27% Number with an unused LUT: 2,073 out of 8,097 25%
Number of fully used LUT-FF pairs: 3,819 out of 7,910 48% Number of fully used LUT-FF pairs: 3,929 out of 8,097 48%
Number of unique control sets: 237 Number of unique control sets: 251
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 548 out of 54,576 1% to control set restrictions: 532 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of one Flip Flop within a slice. A control set is a unique combination of
...@@ -59,12 +59,12 @@ Slice Logic Distribution: ...@@ -59,12 +59,12 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails. over-mapped for a non-slice resource or if Placement fails.
IO Utilization: IO Utilization:
Number of bonded IOBs: 188 out of 296 63% Number of bonded IOBs: 192 out of 296 64%
Number of LOCed IOBs: 188 out of 188 100% Number of LOCed IOBs: 192 out of 192 100%
Specific Feature Utilization: Specific Feature Utilization:
Number of RAMB16BWERs: 26 out of 116 22% Number of RAMB16BWERs: 23 out of 116 19%
Number of RAMB8BWERs: 4 out of 232 1% Number of RAMB8BWERs: 7 out of 232 3%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9% Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3 Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0 Number used as BUFIO2_2CLKs: 0
...@@ -100,11 +100,11 @@ Specific Feature Utilization: ...@@ -100,11 +100,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.80 Average Fanout of Non-Clock Nets: 3.73
Peak Memory Usage: 409 MB Peak Memory Usage: 415 MB
Total REAL time to MAP completion: 4 mins 52 secs Total REAL time to MAP completion: 5 mins 2 secs
Total CPU time to MAP completion (all processors): 4 mins 43 secs Total CPU time to MAP completion (all processors): 4 mins 55 secs
Table of Contents Table of Contents
----------------- -----------------
...@@ -127,6 +127,9 @@ Section 1 - Errors ...@@ -127,6 +127,9 @@ Section 1 - Errors
Section 2 - Warnings Section 2 - Warnings
-------------------- --------------------
WARNING:Security:42 - Your license support version '2014.04' for ISE expires in
4 days after which you will not qualify for Xilinx software updates or new
releases.
WARNING:MapLib:701 - Signal L_CLKp connected to top level port L_CLKp has been WARNING:MapLib:701 - Signal L_CLKp connected to top level port L_CLKp has been
removed. removed.
WARNING:MapLib:701 - Signal L_CLKn connected to top level port L_CLKn has been WARNING:MapLib:701 - Signal L_CLKn connected to top level port L_CLKn has been
...@@ -159,13 +162,14 @@ Section 3 - Informational ...@@ -159,13 +162,14 @@ Section 3 - Informational
INFO:Map:284 - Map is running with the multi-threading option on. Map currently INFO:Map:284 - Map is running with the multi-threading option on. Map currently
supports the use of up to 2 processors. Based on the the user options and supports the use of up to 2 processors. Based on the the user options and
machine load, Map will use 2 processors during this run. machine load, Map will use 2 processors during this run.
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
INFO:LIT:243 - Logical network INFO:LIT:243 - Logical network
cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3 cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3
_infrastructure_inst/rst0_sync_r<24> has no load. _infrastructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 8 more times for the following INFO:LIT:395 - The above info message is repeated 8 more times for the following
(max. 5 shown): (max. 5 shown):
N798, N776,
N800, N778,
aux_buttons_i<1>_IBUF, aux_buttons_i<1>_IBUF,
aux_buttons_i<0>_IBUF, aux_buttons_i<0>_IBUF,
P_WR_REQ<1>_IBUF P_WR_REQ<1>_IBUF
...@@ -186,7 +190,7 @@ INFO:Pack:1650 - Map created a placed design. ...@@ -186,7 +190,7 @@ INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary Section 4 - Removed Logic Summary
--------------------------------- ---------------------------------
93 block(s) removed 94 block(s) removed
2 block(s) optimized away 2 block(s) optimized away
74 signal(s) removed 74 signal(s) removed
...@@ -378,6 +382,9 @@ nfrastructure_inst/syn_clk0_powerup_pll_locked" (FF) removed. ...@@ -378,6 +382,9 @@ nfrastructure_inst/syn_clk0_powerup_pll_locked" (FF) removed.
Loadless block "cmp_clk_250_buf" (CKBUF) removed. Loadless block "cmp_clk_250_buf" (CKBUF) removed.
The signal "sys_clk_250_buf" is loadless and has been removed. The signal "sys_clk_250_buf" is loadless and has been removed.
Loadless block Loadless block
"cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/Madd_pre_trig_value[31]_GND_383_
o_add_67_OUT31" (ROM) removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[0].loop3.iodelay_m" (IODELAY2) "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[0].loop3.iodelay_m" (IODELAY2)
removed. removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master" is loadless The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master" is loadless
...@@ -803,6 +810,10 @@ Section 6 - IOB Properties ...@@ -803,6 +810,10 @@ Section 6 - IOB Properties
| pcb_ver_i<1> | IOB | INPUT | LVCMOS15 | | | | | | | | pcb_ver_i<1> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<2> | IOB | INPUT | LVCMOS15 | | | | | | | | pcb_ver_i<2> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<3> | IOB | INPUT | LVCMOS15 | | | | | | | | pcb_ver_i<3> | IOB | INPUT | LVCMOS15 | | | | | | |
| pll20dac_sync_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll25dac_sync_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| plldac_din_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| plldac_sclk_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs Section 7 - RPMs
......
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